1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  ; Function Attrs: nofree norecurse nounwind
6  define dso_local void @test(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) local_unnamed_addr #0 {
7  bb:
8    %tmp = icmp eq i32 %arg2, 0
9    %tmp1 = add i32 %arg2, 3
10    %tmp2 = lshr i32 %tmp1, 2
11    %tmp3 = shl nuw i32 %tmp2, 2
12    %tmp4 = add i32 %tmp3, -4
13    %tmp5 = lshr i32 %tmp4, 2
14    %tmp6 = add nuw nsw i32 %tmp5, 1
15    %conv.mask = zext i16 %mask to i32
16    %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask)
17    br i1 %tmp, label %bb27, label %bb3
18
19  bb3:                                              ; preds = %bb
20    %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6)
21    br label %bb9
22
23  bb9:                                              ; preds = %bb9, %bb3
24    %lsr.iv2 = phi i32* [ %scevgep3, %bb9 ], [ %arg1, %bb3 ]
25    %lsr.iv = phi i32* [ %scevgep, %bb9 ], [ %arg, %bb3 ]
26    %tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ]
27    %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ]
28    %lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>*
29    %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
30    %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8)
31    %and = and <4 x i1> %vctp, %invariant.mask
32    %tmp11 = sub i32 %tmp8, 4
33    %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef)
34    %tmp18 = icmp ne <4 x i32> %tmp17, zeroinitializer
35    %tmp20 = and <4 x i1> %tmp18, %vctp
36    %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %tmp20, <4 x i32> undef)
37    %tmp23 = mul nsw <4 x i32> %tmp22, %tmp17
38    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp23, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %tmp20)
39    %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1)
40    %tmp13 = icmp ne i32 %tmp12, 0
41    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
42    %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 4
43    br i1 %tmp13, label %bb9, label %bb27
44
45  bb27:                                             ; preds = %bb9, %bb
46    ret void
47  }
48  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
49  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
50  declare i32 @llvm.start.loop.iterations.i32(i32)
51  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
52  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
53  declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
54
55...
56---
57name:            test
58alignment:       2
59exposesReturnsTwice: false
60legalized:       false
61regBankSelected: false
62selected:        false
63failedISel:      false
64tracksRegLiveness: true
65hasWinCFI:       false
66registers:       []
67liveins:
68  - { reg: '$r0', virtual-reg: '' }
69  - { reg: '$r1', virtual-reg: '' }
70  - { reg: '$r2', virtual-reg: '' }
71  - { reg: '$r3', virtual-reg: '' }
72frameInfo:
73  isFrameAddressTaken: false
74  isReturnAddressTaken: false
75  hasStackMap:     false
76  hasPatchPoint:   false
77  stackSize:       12
78  offsetAdjustment: -4
79  maxAlignment:    4
80  adjustsStack:    false
81  hasCalls:        false
82  stackProtector:  ''
83  maxCallFrameSize: 0
84  cvBytesOfCalleeSavedRegisters: 0
85  hasOpaqueSPAdjustment: false
86  hasVAStart:      false
87  hasMustTailInVarArgFunc: false
88  localFrameSize:  0
89  savePoint:       ''
90  restorePoint:    ''
91fixedStack:      []
92stack:
93  - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
94      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
95      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
96  - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
97      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
98      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
99  - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
100      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
101      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
102callSites:       []
103constants:       []
104machineFunctionInfo: {}
105body:             |
106  ; CHECK-LABEL: name: test
107  ; CHECK: bb.0.bb:
108  ; CHECK:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
109  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
110  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
111  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
112  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
113  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
114  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
115  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
116  ; CHECK:   $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
117  ; CHECK:   tCBZ $r2, %bb.3
118  ; CHECK: bb.1.bb3:
119  ; CHECK:   successors: %bb.2(0x80000000)
120  ; CHECK:   liveins: $r0, $r1, $r2, $r3
121  ; CHECK:   $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg
122  ; CHECK:   VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
123  ; CHECK:   $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
124  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
125  ; CHECK: bb.2.bb9:
126  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
127  ; CHECK:   liveins: $lr, $r0, $r1, $r3
128  ; CHECK:   renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
129  ; CHECK:   MVE_VPST 8, implicit $vpr
130  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
131  ; CHECK:   MVE_VPTv4i32r 8, renamable $q0, $zr, 1, implicit-def $vpr
132  ; CHECK:   renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
133  ; CHECK:   renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
134  ; CHECK:   MVE_VPST 8, implicit $vpr
135  ; CHECK:   MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
136  ; CHECK:   $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
137  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
138  ; CHECK: bb.3.bb27:
139  ; CHECK:   $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
140  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
141  bb.0.bb:
142    successors: %bb.3(0x30000000), %bb.1(0x50000000)
143    liveins: $r0, $r1, $r2, $r3, $lr
144
145    frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
146    frame-setup CFI_INSTRUCTION def_cfa_offset 8
147    frame-setup CFI_INSTRUCTION offset $lr, -4
148    frame-setup CFI_INSTRUCTION offset $r7, -8
149    $r7 = frame-setup tMOVr $sp, 14, $noreg
150    frame-setup CFI_INSTRUCTION def_cfa_register $r7
151    $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
152    tCBZ $r2, %bb.3
153
154  bb.1.bb3:
155    successors: %bb.2(0x80000000)
156    liveins: $r0, $r1, $r2, $r3
157
158    renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg
159    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
160    renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
161    $vpr = VMSR_P0 killed $r3, 14, $noreg
162    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
163    VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
164    $r3 = tMOVr $r0, 14, $noreg
165    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
166    $lr = t2DoLoopStart renamable $lr
167
168  bb.2.bb9:
169    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
170    liveins: $lr, $r0, $r1, $r2, $r3
171
172    renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
173    MVE_VPST 4, implicit $vpr
174    renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
175    renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
176    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
177    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
178    MVE_VPST 4, implicit $vpr
179    renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr
180    renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
181    renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
182    MVE_VPST 8, implicit $vpr
183    MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
184    renamable $lr = t2LoopDec killed renamable $lr, 1
185    $r0 = tMOVr $r3, 14, $noreg
186    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
187    tB %bb.3, 14, $noreg
188
189  bb.3.bb27:
190    $sp = tADDspi $sp, 1, 14, $noreg
191    tPOP_RET 14, $noreg, def $r7, def $pc
192
193...
194