1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s 3--- | 4 ; Function Attrs: nofree norecurse nounwind 5 define dso_local void @test_vldr_p0(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) local_unnamed_addr #0 { 6 bb: 7 %tmp = icmp eq i32 %arg2, 0 8 %tmp1 = add i32 %arg2, 3 9 %tmp2 = lshr i32 %tmp1, 2 10 %tmp3 = shl nuw i32 %tmp2, 2 11 %tmp4 = add i32 %tmp3, -4 12 %tmp5 = lshr i32 %tmp4, 2 13 %tmp6 = add nuw nsw i32 %tmp5, 1 14 %conv.mask = zext i16 %mask to i32 15 %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask) 16 br i1 %tmp, label %bb27, label %bb3 17 18 bb3: ; preds = %bb 19 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6) 20 br label %bb9 21 22 bb9: ; preds = %bb9, %bb3 23 %lsr.iv2 = phi i32* [ %scevgep3, %bb9 ], [ %arg1, %bb3 ] 24 %lsr.iv = phi i32* [ %scevgep, %bb9 ], [ %arg, %bb3 ] 25 %tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ] 26 %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ] 27 %lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>* 28 %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>* 29 %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8) 30 %and = and <4 x i1> %vctp, %invariant.mask 31 %tmp11 = sub i32 %tmp8, 4 32 %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef) 33 %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef) 34 %tmp23 = mul nsw <4 x i32> %tmp22, %tmp17 35 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp23, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %and) 36 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1) 37 %tmp13 = icmp ne i32 %tmp12, 0 38 %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 39 %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 4 40 br i1 %tmp13, label %bb9, label %bb27 41 42 bb27: ; preds = %bb9, %bb 43 ret void 44 } 45 46 define dso_local void @test_vstr_p0(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) { 47 bb: 48 unreachable 49 bb3: ; preds = %bb 50 unreachable 51 bb9: ; preds = %bb9, %bb3 52 unreachable 53 bb27: ; preds = %bb9, %bb 54 ret void 55 } 56 57 define dso_local void @test_vmsr_p0(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) { 58 bb: 59 unreachable 60 bb3: ; preds = %bb 61 unreachable 62 bb9: ; preds = %bb9, %bb3 63 unreachable 64 bb27: ; preds = %bb9, %bb 65 ret void 66 } 67 68 define dso_local void @test_vmrs_p0(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) { 69 bb: 70 unreachable 71 bb3: ; preds = %bb 72 unreachable 73 bb9: ; preds = %bb9, %bb3 74 unreachable 75 bb27: ; preds = %bb9, %bb 76 ret void 77 } 78 79 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #1 80 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2 81 declare i32 @llvm.start.loop.iterations.i32(i32) #3 82 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3 83 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4 84 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #4 85 86... 87--- 88name: test_vldr_p0 89alignment: 2 90exposesReturnsTwice: false 91legalized: false 92regBankSelected: false 93selected: false 94failedISel: false 95tracksRegLiveness: true 96hasWinCFI: false 97registers: [] 98liveins: 99 - { reg: '$r0', virtual-reg: '' } 100 - { reg: '$r1', virtual-reg: '' } 101 - { reg: '$r2', virtual-reg: '' } 102 - { reg: '$r3', virtual-reg: '' } 103frameInfo: 104 isFrameAddressTaken: false 105 isReturnAddressTaken: false 106 hasStackMap: false 107 hasPatchPoint: false 108 stackSize: 12 109 offsetAdjustment: -4 110 maxAlignment: 4 111 adjustsStack: false 112 hasCalls: false 113 stackProtector: '' 114 maxCallFrameSize: 0 115 cvBytesOfCalleeSavedRegisters: 0 116 hasOpaqueSPAdjustment: false 117 hasVAStart: false 118 hasMustTailInVarArgFunc: false 119 localFrameSize: 0 120 savePoint: '' 121 restorePoint: '' 122fixedStack: [] 123stack: 124 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 125 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 126 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 127 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 128 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 129 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 130 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 131 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 132 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 133callSites: [] 134constants: [] 135machineFunctionInfo: {} 136body: | 137 ; CHECK-LABEL: name: test_vldr_p0 138 ; CHECK: bb.0.bb: 139 ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) 140 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 141 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 142 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 143 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 144 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 145 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 146 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 147 ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 148 ; CHECK: tCBZ $r2, %bb.3 149 ; CHECK: bb.1.bb3: 150 ; CHECK: successors: %bb.2(0x80000000) 151 ; CHECK: liveins: $r0, $r1, $r2, $r3 152 ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 153 ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 154 ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 155 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 156 ; CHECK: bb.2.bb9: 157 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 158 ; CHECK: liveins: $lr, $r0, $r1, $r3 159 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 160 ; CHECK: MVE_VPST 4, implicit $vpr 161 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) 162 ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) 163 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 164 ; CHECK: MVE_VPST 8, implicit $vpr 165 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) 166 ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 167 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 168 ; CHECK: bb.3.bb27: 169 ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 170 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 171 bb.0.bb: 172 successors: %bb.3(0x30000000), %bb.1(0x50000000) 173 liveins: $r0, $r1, $r2, $r3, $lr 174 175 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 176 frame-setup CFI_INSTRUCTION def_cfa_offset 8 177 frame-setup CFI_INSTRUCTION offset $lr, -4 178 frame-setup CFI_INSTRUCTION offset $r7, -8 179 $r7 = frame-setup tMOVr $sp, 14, $noreg 180 frame-setup CFI_INSTRUCTION def_cfa_register $r7 181 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 182 tCBZ $r2, %bb.3 183 184 bb.1.bb3: 185 successors: %bb.2(0x80000000) 186 liveins: $r0, $r1, $r2, $r3 187 188 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 189 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 190 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 191 $vpr = VMSR_P0 killed $r3, 14, $noreg 192 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 193 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) 194 $r3 = tMOVr $r0, 14, $noreg 195 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 196 $lr = t2DoLoopStart renamable $lr 197 198 bb.2.bb9: 199 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 200 liveins: $lr, $r0, $r1, $r2, $r3 201 202 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) 203 MVE_VPST 2, implicit $vpr 204 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 205 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) 206 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) 207 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 208 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 209 MVE_VPST 8, implicit $vpr 210 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) 211 renamable $lr = t2LoopDec killed renamable $lr, 1 212 $r0 = tMOVr $r3, 14, $noreg 213 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 214 tB %bb.3, 14, $noreg 215 216 bb.3.bb27: 217 $sp = tADDspi $sp, 1, 14, $noreg 218 tPOP_RET 14, $noreg, def $r7, def $pc 219 220... 221--- 222name: test_vstr_p0 223alignment: 2 224exposesReturnsTwice: false 225legalized: false 226regBankSelected: false 227selected: false 228failedISel: false 229tracksRegLiveness: true 230hasWinCFI: false 231registers: [] 232liveins: 233 - { reg: '$r0', virtual-reg: '' } 234 - { reg: '$r1', virtual-reg: '' } 235 - { reg: '$r2', virtual-reg: '' } 236 - { reg: '$r3', virtual-reg: '' } 237frameInfo: 238 isFrameAddressTaken: false 239 isReturnAddressTaken: false 240 hasStackMap: false 241 hasPatchPoint: false 242 stackSize: 12 243 offsetAdjustment: -4 244 maxAlignment: 4 245 adjustsStack: false 246 hasCalls: false 247 stackProtector: '' 248 maxCallFrameSize: 0 249 cvBytesOfCalleeSavedRegisters: 0 250 hasOpaqueSPAdjustment: false 251 hasVAStart: false 252 hasMustTailInVarArgFunc: false 253 localFrameSize: 0 254 savePoint: '' 255 restorePoint: '' 256fixedStack: [] 257stack: 258 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 259 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 260 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 261 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 262 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 263 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 264 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 265 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 266 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 267callSites: [] 268constants: [] 269machineFunctionInfo: {} 270body: | 271 ; CHECK-LABEL: name: test_vstr_p0 272 ; CHECK: bb.0.bb: 273 ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) 274 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 275 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 276 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 277 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 278 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 279 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 280 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 281 ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 282 ; CHECK: tCBZ $r2, %bb.3 283 ; CHECK: bb.1.bb3: 284 ; CHECK: successors: %bb.2(0x80000000) 285 ; CHECK: liveins: $r0, $r1, $r2, $r3 286 ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 287 ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 288 ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 289 ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 290 ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 291 ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 292 ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 293 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 294 ; CHECK: $lr = t2DLS killed renamable $lr 295 ; CHECK: bb.2.bb9: 296 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 297 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 298 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 299 ; CHECK: MVE_VPST 2, implicit $vpr 300 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 301 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr 302 ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr 303 ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 304 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 305 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 306 ; CHECK: MVE_VPST 8, implicit $vpr 307 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr 308 ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 309 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 310 ; CHECK: bb.3.bb27: 311 ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 312 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 313 bb.0.bb: 314 successors: %bb.3(0x30000000), %bb.1(0x50000000) 315 liveins: $r0, $r1, $r2, $r3, $lr 316 317 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 318 frame-setup CFI_INSTRUCTION def_cfa_offset 8 319 frame-setup CFI_INSTRUCTION offset $lr, -4 320 frame-setup CFI_INSTRUCTION offset $r7, -8 321 $r7 = frame-setup tMOVr $sp, 14, $noreg 322 frame-setup CFI_INSTRUCTION def_cfa_register $r7 323 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 324 tCBZ $r2, %bb.3 325 326 bb.1.bb3: 327 successors: %bb.2(0x80000000) 328 liveins: $r0, $r1, $r2, $r3 329 330 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 331 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 332 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 333 $vpr = VMSR_P0 killed $r3, 14, $noreg 334 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 335 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) 336 $r3 = tMOVr $r0, 14, $noreg 337 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 338 $lr = t2DoLoopStart renamable $lr 339 340 bb.2.bb9: 341 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 342 liveins: $lr, $r0, $r1, $r2, $r3 343 344 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) 345 MVE_VPST 2, implicit $vpr 346 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 347 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr 348 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr 349 VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) 350 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 351 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 352 MVE_VPST 8, implicit $vpr 353 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr 354 renamable $lr = t2LoopDec killed renamable $lr, 1 355 $r0 = tMOVr $r3, 14, $noreg 356 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 357 tB %bb.3, 14, $noreg 358 359 bb.3.bb27: 360 $sp = tADDspi $sp, 1, 14, $noreg 361 tPOP_RET 14, $noreg, def $r7, def $pc 362 363... 364--- 365name: test_vmsr_p0 366alignment: 2 367exposesReturnsTwice: false 368legalized: false 369regBankSelected: false 370selected: false 371failedISel: false 372tracksRegLiveness: true 373hasWinCFI: false 374registers: [] 375liveins: 376 - { reg: '$r0', virtual-reg: '' } 377 - { reg: '$r1', virtual-reg: '' } 378 - { reg: '$r2', virtual-reg: '' } 379 - { reg: '$r3', virtual-reg: '' } 380frameInfo: 381 isFrameAddressTaken: false 382 isReturnAddressTaken: false 383 hasStackMap: false 384 hasPatchPoint: false 385 stackSize: 12 386 offsetAdjustment: -4 387 maxAlignment: 4 388 adjustsStack: false 389 hasCalls: false 390 stackProtector: '' 391 maxCallFrameSize: 0 392 cvBytesOfCalleeSavedRegisters: 0 393 hasOpaqueSPAdjustment: false 394 hasVAStart: false 395 hasMustTailInVarArgFunc: false 396 localFrameSize: 0 397 savePoint: '' 398 restorePoint: '' 399fixedStack: [] 400stack: 401 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 402 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 403 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 404 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 405 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 406 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 407 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 408 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 409 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 410callSites: [] 411constants: [] 412machineFunctionInfo: {} 413body: | 414 ; CHECK-LABEL: name: test_vmsr_p0 415 ; CHECK: bb.0.bb: 416 ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) 417 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 418 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 419 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 420 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 421 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 422 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 423 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 424 ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 425 ; CHECK: tCBZ $r2, %bb.3 426 ; CHECK: bb.1.bb3: 427 ; CHECK: successors: %bb.2(0x80000000) 428 ; CHECK: liveins: $r0, $r1, $r2, $r3 429 ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 430 ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 431 ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 432 ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 433 ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 434 ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 435 ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 436 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 437 ; CHECK: $lr = t2DLS killed renamable $lr 438 ; CHECK: bb.2.bb9: 439 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 440 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 441 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 442 ; CHECK: MVE_VPST 2, implicit $vpr 443 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 444 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr 445 ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr 446 ; CHECK: $vpr = VMSR_P0 $r3, 14 /* CC::al */, $noreg 447 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 448 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 449 ; CHECK: MVE_VPST 8, implicit $vpr 450 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr 451 ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 452 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 453 ; CHECK: bb.3.bb27: 454 ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 455 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 456 bb.0.bb: 457 successors: %bb.3(0x30000000), %bb.1(0x50000000) 458 liveins: $r0, $r1, $r2, $r3, $lr 459 460 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 461 frame-setup CFI_INSTRUCTION def_cfa_offset 8 462 frame-setup CFI_INSTRUCTION offset $lr, -4 463 frame-setup CFI_INSTRUCTION offset $r7, -8 464 $r7 = frame-setup tMOVr $sp, 14, $noreg 465 frame-setup CFI_INSTRUCTION def_cfa_register $r7 466 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 467 tCBZ $r2, %bb.3 468 469 bb.1.bb3: 470 successors: %bb.2(0x80000000) 471 liveins: $r0, $r1, $r2, $r3 472 473 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 474 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 475 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 476 $vpr = VMSR_P0 killed $r3, 14, $noreg 477 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 478 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) 479 $r3 = tMOVr $r0, 14, $noreg 480 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 481 $lr = t2DoLoopStart renamable $lr 482 483 bb.2.bb9: 484 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 485 liveins: $lr, $r0, $r1, $r2, $r3 486 487 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) 488 MVE_VPST 2, implicit $vpr 489 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 490 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr 491 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr 492 $vpr = VMSR_P0 $r3, 14, $noreg 493 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 494 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 495 MVE_VPST 8, implicit $vpr 496 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr 497 renamable $lr = t2LoopDec killed renamable $lr, 1 498 $r0 = tMOVr $r3, 14, $noreg 499 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 500 tB %bb.3, 14, $noreg 501 502 bb.3.bb27: 503 $sp = tADDspi $sp, 1, 14, $noreg 504 tPOP_RET 14, $noreg, def $r7, def $pc 505 506... 507--- 508name: test_vmrs_p0 509alignment: 2 510exposesReturnsTwice: false 511legalized: false 512regBankSelected: false 513selected: false 514failedISel: false 515tracksRegLiveness: true 516hasWinCFI: false 517registers: [] 518liveins: 519 - { reg: '$r0', virtual-reg: '' } 520 - { reg: '$r1', virtual-reg: '' } 521 - { reg: '$r2', virtual-reg: '' } 522 - { reg: '$r3', virtual-reg: '' } 523frameInfo: 524 isFrameAddressTaken: false 525 isReturnAddressTaken: false 526 hasStackMap: false 527 hasPatchPoint: false 528 stackSize: 12 529 offsetAdjustment: -4 530 maxAlignment: 4 531 adjustsStack: false 532 hasCalls: false 533 stackProtector: '' 534 maxCallFrameSize: 0 535 cvBytesOfCalleeSavedRegisters: 0 536 hasOpaqueSPAdjustment: false 537 hasVAStart: false 538 hasMustTailInVarArgFunc: false 539 localFrameSize: 0 540 savePoint: '' 541 restorePoint: '' 542fixedStack: [] 543stack: 544 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 545 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 546 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 547 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 548 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 549 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 550 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 551 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 552 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 553callSites: [] 554constants: [] 555machineFunctionInfo: {} 556body: | 557 ; CHECK-LABEL: name: test_vmrs_p0 558 ; CHECK: bb.0.bb: 559 ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) 560 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 561 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 562 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 563 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 564 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 565 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 566 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 567 ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 568 ; CHECK: tCBZ $r2, %bb.3 569 ; CHECK: bb.1.bb3: 570 ; CHECK: successors: %bb.2(0x80000000) 571 ; CHECK: liveins: $r0, $r1, $r2, $r3 572 ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 573 ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 574 ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 575 ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 576 ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 577 ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 578 ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 579 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 580 ; CHECK: $lr = t2DLS killed renamable $lr 581 ; CHECK: bb.2.bb9: 582 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 583 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 584 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 585 ; CHECK: MVE_VPST 2, implicit $vpr 586 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 587 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr 588 ; CHECK: dead renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr 589 ; CHECK: $r3 = VMRS_P0 $vpr, 14 /* CC::al */, $noreg 590 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 591 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 592 ; CHECK: MVE_VPST 8, implicit $vpr 593 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr 594 ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 595 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 596 ; CHECK: bb.3.bb27: 597 ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 598 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 599 bb.0.bb: 600 successors: %bb.3(0x30000000), %bb.1(0x50000000) 601 liveins: $r0, $r1, $r2, $r3, $lr 602 603 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 604 frame-setup CFI_INSTRUCTION def_cfa_offset 8 605 frame-setup CFI_INSTRUCTION offset $lr, -4 606 frame-setup CFI_INSTRUCTION offset $r7, -8 607 $r7 = frame-setup tMOVr $sp, 14, $noreg 608 frame-setup CFI_INSTRUCTION def_cfa_register $r7 609 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 610 tCBZ $r2, %bb.3 611 612 bb.1.bb3: 613 successors: %bb.2(0x80000000) 614 liveins: $r0, $r1, $r2, $r3 615 616 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 617 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 618 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 619 $vpr = VMSR_P0 killed $r3, 14, $noreg 620 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 621 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) 622 $r3 = tMOVr $r0, 14, $noreg 623 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 624 $lr = t2DoLoopStart renamable $lr 625 626 bb.2.bb9: 627 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 628 liveins: $lr, $r0, $r1, $r2, $r3 629 630 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) 631 MVE_VPST 2, implicit $vpr 632 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 633 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr 634 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr 635 $r3 = VMRS_P0 $vpr, 14, $noreg 636 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 637 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 638 MVE_VPST 8, implicit $vpr 639 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr 640 renamable $lr = t2LoopDec killed renamable $lr, 1 641 $r0 = tMOVr $r3, 14, $noreg 642 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 643 tB %bb.3, 14, $noreg 644 645 bb.3.bb27: 646 $sp = tADDspi $sp, 1, 14, $noreg 647 tPOP_RET 14, $noreg, def $r7, def $pc 648 649... 650