1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  define dso_local void @vctp_tsubi3(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
6  entry:
7    %cmp8 = icmp sgt i32 %N, 0
8    %0 = add i32 %N, 3
9    %1 = lshr i32 %0, 2
10    %2 = shl nuw i32 %1, 2
11    %3 = add i32 %2, -4
12    %4 = lshr i32 %3, 2
13    %5 = add nuw nsw i32 %4, 1
14    br i1 %cmp8, label %vector.ph, label %for.cond.cleanup
15
16  vector.ph:                                        ; preds = %entry
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
18    br label %vector.body
19
20  vector.body:                                      ; preds = %vector.body, %vector.ph
21    %lsr.iv17 = phi i32* [ %scevgep18, %vector.body ], [ %A, %vector.ph ]
22    %lsr.iv14 = phi i32* [ %scevgep15, %vector.body ], [ %C, %vector.ph ]
23    %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %B, %vector.ph ]
24    %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ]
25    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
26    %lsr.iv13 = bitcast i32* %lsr.iv to <4 x i32>*
27    %lsr.iv1416 = bitcast i32* %lsr.iv14 to <4 x i32>*
28    %lsr.iv1719 = bitcast i32* %lsr.iv17 to <4 x i32>*
29    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
30    %9 = sub i32 %7, 5
31    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef)
32    %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef)
33    %10 = add nsw <4 x i32> %wide.masked.load12, %wide.masked.load
34    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %10, <4 x i32>* %lsr.iv1719, i32 4, <4 x i1> %8)
35    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
36    %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4
37    %scevgep18 = getelementptr i32, i32* %lsr.iv17, i32 4
38    %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
39    %12 = icmp ne i32 %11, 0
40    br i1 %12, label %vector.body, label %for.cond.cleanup
41
42  for.cond.cleanup:                                 ; preds = %vector.body, %entry
43    ret void
44  }
45  declare i32 @llvm.start.loop.iterations.i32(i32)
46  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
47  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
48  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
49  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
50
51...
52---
53name:            vctp_tsubi3
54alignment:       2
55exposesReturnsTwice: false
56legalized:       false
57regBankSelected: false
58selected:        false
59failedISel:      false
60tracksRegLiveness: true
61hasWinCFI:       false
62registers:       []
63liveins:
64  - { reg: '$r0', virtual-reg: '' }
65  - { reg: '$r1', virtual-reg: '' }
66  - { reg: '$r2', virtual-reg: '' }
67  - { reg: '$r3', virtual-reg: '' }
68frameInfo:
69  isFrameAddressTaken: false
70  isReturnAddressTaken: false
71  hasStackMap:     false
72  hasPatchPoint:   false
73  stackSize:       8
74  offsetAdjustment: 0
75  maxAlignment:    4
76  adjustsStack:    false
77  hasCalls:        false
78  stackProtector:  ''
79  maxCallFrameSize: 0
80  cvBytesOfCalleeSavedRegisters: 0
81  hasOpaqueSPAdjustment: false
82  hasVAStart:      false
83  hasMustTailInVarArgFunc: false
84  localFrameSize:  0
85  savePoint:       ''
86  restorePoint:    ''
87fixedStack:      []
88stack:
89  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
90      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
91      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
92  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
93      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
94      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
95callSites:       []
96constants:       []
97machineFunctionInfo: {}
98body:             |
99  ; CHECK-LABEL: name: vctp_tsubi3
100  ; CHECK: bb.0.entry:
101  ; CHECK:   successors: %bb.1(0x80000000)
102  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r7
103  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
104  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
105  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
106  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
107  ; CHECK:   tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
108  ; CHECK:   t2IT 11, 8, implicit-def $itstate
109  ; CHECK:   tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
110  ; CHECK: bb.1.vector.ph:
111  ; CHECK:   successors: %bb.2(0x80000000)
112  ; CHECK:   liveins: $r0, $r1, $r2, $r3
113  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
114  ; CHECK: bb.2.vector.body:
115  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
116  ; CHECK:   liveins: $lr, $r0, $r1, $r2
117  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4)
118  ; CHECK:   renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4)
119  ; CHECK:   renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
120  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4)
121  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
122  ; CHECK: bb.3.for.cond.cleanup:
123  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
124  bb.0.entry:
125    successors: %bb.1(0x80000000)
126    liveins: $r0, $r1, $r2, $r3, $r7, $lr
127
128    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
129    frame-setup CFI_INSTRUCTION def_cfa_offset 8
130    frame-setup CFI_INSTRUCTION offset $lr, -4
131    frame-setup CFI_INSTRUCTION offset $r7, -8
132    tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr
133    t2IT 11, 8, implicit-def $itstate
134    tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate
135
136  bb.1.vector.ph:
137    successors: %bb.2(0x80000000)
138    liveins: $r0, $r1, $r2, $r3, $r7, $lr
139
140    renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
141    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
142    renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
143    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
144    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
145    $lr = t2DoLoopStart renamable $lr
146
147  bb.2.vector.body:
148    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
149    liveins: $lr, $r0, $r1, $r2, $r3
150
151    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
152    MVE_VPST 4, implicit $vpr
153    renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
154    renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
155    renamable $r3 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
156    renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
157    MVE_VPST 8, implicit $vpr
158    renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
159    renamable $lr = t2LoopDec killed renamable $lr, 1
160    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
161    tB %bb.3, 14, $noreg
162
163  bb.3.for.cond.cleanup:
164    tPOP_RET 14, $noreg, def $r7, def $pc
165
166...
167