1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  define hidden i32 @arm_elementwise_mul_s8(i8* %input_1_vect, i8* %input_2_vect, i32 %input_1_offset, i32 %input_2_offset, i8* %output, i32 %out_offset, i32 %out_mult, i32 %out_shift, i32 %out_activation_min, i32 %out_activation_max, i32 %block_size) local_unnamed_addr #0 {
6  entry:
7    %add = add i32 %block_size, 3
8    %div = lshr i32 %add, 2
9    %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %div)
10    br i1 %0, label %for.body.lr.ph, label %for.cond.cleanup
11
12  for.body.lr.ph:                                   ; preds = %entry
13    %.splatinsert.i41 = insertelement <4 x i32> undef, i32 %out_activation_min, i32 0
14    %.splat.i42 = shufflevector <4 x i32> %.splatinsert.i41, <4 x i32> undef, <4 x i32> zeroinitializer
15    %.splatinsert.i = insertelement <4 x i32> undef, i32 %out_activation_max, i32 0
16    %.splat.i = shufflevector <4 x i32> %.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
17    br label %for.body
18
19  for.cond.cleanup:                                 ; preds = %for.body, %entry
20    ret i32 0
21
22  for.body:                                         ; preds = %for.body, %for.body.lr.ph
23    %input_1_vect.addr.052 = phi i8* [ %input_1_vect, %for.body.lr.ph ], [ %add.ptr, %for.body ]
24    %input_2_vect.addr.051 = phi i8* [ %input_2_vect, %for.body.lr.ph ], [ %add.ptr14, %for.body ]
25    %output.addr.050 = phi i8* [ %output, %for.body.lr.ph ], [ %add.ptr15, %for.body ]
26    %num_elements.049 = phi i32 [ %block_size, %for.body.lr.ph ], [ %sub, %for.body ]
27    %iv = phi i32 [ %div, %for.body.lr.ph ], [ %iv.next, %for.body ]
28    %output_cast = bitcast i8* %output.addr.050 to <4 x i32>*
29    %input_2_cast = bitcast i8* %input_2_vect.addr.051 to <4 x i32>*
30    %input_1_cast = bitcast i8* %input_1_vect.addr.052 to <4 x i32>*
31    %pred = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %num_elements.049)
32    %load.1 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_1_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)
33    %insert.input_1_offset = insertelement <4 x i32> undef, i32 %input_1_offset, i32 0
34    %splat.input_1_offset = shufflevector <4 x i32> %insert.input_1_offset, <4 x i32> undef, <4 x i32> zeroinitializer
35    %insert.input_2_offset = insertelement <4 x i32> undef, i32 %input_2_offset, i32 0
36    %splat.input_2_offset = shufflevector <4 x i32> %insert.input_2_offset, <4 x i32> undef, <4 x i32> zeroinitializer
37    %add.1 = add <4 x i32> %load.1, %splat.input_1_offset
38    %load.2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_2_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)
39    %add.2 = add <4 x i32> %load.2, %splat.input_2_offset
40    %mul = mul <4 x i32> %add.1, %add.2
41    %insert.output = insertelement <4 x i32> undef, i32 %out_offset, i32 0
42    %splat.output = shufflevector <4 x i32> %insert.output, <4 x i32> undef, <4 x i32> zeroinitializer
43    %add7 = add <4 x i32> %mul, %splat.output
44    %max = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %add7, <4 x i32> %.splat.i42, i32 1, <4 x i1> %pred, <4 x i32> undef)
45    %min = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %max, <4 x i32> %.splat.i, i32 1, <4 x i1> %pred, <4 x i32> undef)
46    tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %min, <4 x i32>* %output_cast, i32 4, <4 x i1> %pred)
47    %add.ptr = getelementptr inbounds i8, i8* %input_1_vect.addr.052, i32 4
48    %add.ptr14 = getelementptr inbounds i8, i8* %input_2_vect.addr.051, i32 4
49    %add.ptr15 = getelementptr inbounds i8, i8* %output.addr.050, i32 4
50    %sub = add i32 %num_elements.049, -4
51    %iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %iv, i32 1)
52    %cmp = icmp ne i32 %iv.next, 0
53    br i1 %cmp, label %for.body, label %for.cond.cleanup
54  }
55  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
56  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
57  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #3
58  declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
59  declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
60  declare i1 @llvm.test.set.loop.iterations.i32(i32) #4
61  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #4
62  declare void @llvm.stackprotector(i8*, i8**) #5
63...
64---
65name:            arm_elementwise_mul_s8
66alignment:       2
67exposesReturnsTwice: false
68legalized:       false
69regBankSelected: false
70selected:        false
71failedISel:      false
72tracksRegLiveness: true
73hasWinCFI:       false
74registers:       []
75liveins:
76  - { reg: '$r0', virtual-reg: '' }
77  - { reg: '$r1', virtual-reg: '' }
78  - { reg: '$r2', virtual-reg: '' }
79  - { reg: '$r3', virtual-reg: '' }
80frameInfo:
81  isFrameAddressTaken: false
82  isReturnAddressTaken: false
83  hasStackMap:     false
84  hasPatchPoint:   false
85  stackSize:       20
86  offsetAdjustment: 0
87  maxAlignment:    4
88  adjustsStack:    false
89  hasCalls:        false
90  stackProtector:  ''
91  maxCallFrameSize: 0
92  cvBytesOfCalleeSavedRegisters: 0
93  hasOpaqueSPAdjustment: false
94  hasVAStart:      false
95  hasMustTailInVarArgFunc: false
96  localFrameSize:  0
97  savePoint:       ''
98  restorePoint:    ''
99fixedStack:
100  - { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default,
101      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
102      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
103  - { id: 1, type: default, offset: 20, size: 4, alignment: 4, stack-id: default,
104      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
105      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
106  - { id: 2, type: default, offset: 16, size: 4, alignment: 8, stack-id: default,
107      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
108      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
109  - { id: 3, type: default, offset: 12, size: 4, alignment: 4, stack-id: default,
110      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
111      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
112  - { id: 4, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
113      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
114      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
115  - { id: 5, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
116      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
117      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
118  - { id: 6, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
119      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
120      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
121stack:
122  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
123      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
124      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
125  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
126      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
127      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
128  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
129      stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
130      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
131  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
132      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
133      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
134  - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
135      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
136      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
137callSites:       []
138constants:       []
139machineFunctionInfo: {}
140body:             |
141  ; CHECK-LABEL: name: arm_elementwise_mul_s8
142  ; CHECK: bb.0.entry:
143  ; CHECK:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
144  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7
145  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
146  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 20
147  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
148  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
149  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r6, -12
150  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r5, -16
151  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -20
152  ; CHECK:   renamable $r12 = t2LDRi12 $sp, 44, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.6, align 8)
153  ; CHECK:   $lr = MVE_WLSTP_32 killed renamable $r12, %bb.3
154  ; CHECK: bb.1.for.body.lr.ph:
155  ; CHECK:   successors: %bb.2(0x80000000)
156  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
157  ; CHECK:   $r7, $r6 = t2LDRDi8 $sp, 36, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5)
158  ; CHECK:   $r5, $r4 = t2LDRDi8 $sp, 20, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1)
159  ; CHECK:   renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q0
160  ; CHECK:   renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, undef renamable $q1
161  ; CHECK: bb.2.for.body:
162  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
163  ; CHECK:   liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5
164  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load 16 from %ir.input_2_cast, align 4)
165  ; CHECK:   renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load 16 from %ir.input_1_cast, align 4)
166  ; CHECK:   renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
167  ; CHECK:   renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
168  ; CHECK:   renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
169  ; CHECK:   renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2
170  ; CHECK:   renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
171  ; CHECK:   renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 0, $noreg, undef renamable $q2
172  ; CHECK:   renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 0, killed $noreg :: (store 16 into %ir.output_cast, align 4)
173  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
174  ; CHECK: bb.3.for.cond.cleanup:
175  ; CHECK:   $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
176  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
177  bb.0.entry:
178    successors: %bb.1(0x40000000), %bb.3(0x40000000)
179    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr
180
181    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
182    frame-setup CFI_INSTRUCTION def_cfa_offset 20
183    frame-setup CFI_INSTRUCTION offset $lr, -4
184    frame-setup CFI_INSTRUCTION offset $r7, -8
185    frame-setup CFI_INSTRUCTION offset $r6, -12
186    frame-setup CFI_INSTRUCTION offset $r5, -16
187    frame-setup CFI_INSTRUCTION offset $r4, -20
188    renamable $r12 = t2LDRi12 $sp, 44, 14, $noreg :: (load 4 from %fixed-stack.0, align 8)
189    renamable $r5 = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
190    renamable $lr = t2LSRri killed renamable $r5, 2, 14, $noreg, $noreg
191    t2WhileLoopStart renamable $lr, %bb.3, implicit-def dead $cpsr
192    tB %bb.1, 14, $noreg
193
194  bb.1.for.body.lr.ph:
195    successors: %bb.2(0x80000000)
196    liveins: $lr, $r0, $r1, $r2, $r3, $r12
197
198    $r7, $r6 = t2LDRDi8 $sp, 36, 14, $noreg :: (load 4 from %fixed-stack.2, align 8), (load 4 from %fixed-stack.1)
199    $r5, $r4 = t2LDRDi8 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.6, align 8), (load 4 from %fixed-stack.5)
200    renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q0
201    renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, undef renamable $q1
202
203  bb.2.for.body:
204    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
205    liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r12
206
207    renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
208    MVE_VPST 8, implicit $vpr
209    renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4)
210    MVE_VPST 8, implicit $vpr
211    renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4)
212    renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
213    renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
214    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
215    renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
216    renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2
217    MVE_VPST 2, implicit $vpr
218    renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2
219    renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, renamable $vpr, undef renamable $q2
220    renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 1, killed renamable $vpr :: (store 16 into %ir.output_cast, align 4)
221    renamable $lr = t2LoopDec killed renamable $lr, 1
222    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
223    tB %bb.3, 14, $noreg
224
225  bb.3.for.cond.cleanup:
226    $r0, dead $cpsr = tMOVi8 0, 14, $noreg
227    tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
228
229...
230