1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 @_ZL3arr = internal global [10 x i32] [i32 1, i32 2, i32 3, i32 5, i32 5, i32 5, i32 -2, i32 0, i32 -8, i32 -1], align 4 6 @.str = private unnamed_addr constant [5 x i8] c"%d, \00", align 1 7 8 define arm_aapcs_vfpcc void @vpt_block(i32* nocapture %A, i32 %n, i32 %x) { 9 entry: 10 %cmp9 = icmp sgt i32 %n, 0 11 %0 = add i32 %n, 3 12 %1 = lshr i32 %0, 2 13 %2 = shl nuw i32 %1, 2 14 %3 = add i32 %2, -4 15 %4 = lshr i32 %3, 2 16 %5 = add nuw nsw i32 %4, 1 17 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup 18 19 vector.ph: ; preds = %entry 20 %sub = sub nsw i32 0, %x 21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 22 br label %vector.body 23 24 vector.body: ; preds = %vector.body, %vector.ph 25 %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %A, %vector.ph ] 26 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ] 27 %7 = phi i32 [ %n, %vector.ph ], [ %9, %vector.body ] 28 %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>* 29 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 30 %9 = sub i32 %7, 4 31 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef) 32 %10 = insertelement <4 x i32> undef, i32 %x, i32 0 33 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer 34 %12 = icmp slt <4 x i32> %wide.masked.load, %11 35 %13 = insertelement <4 x i32> undef, i32 %sub, i32 0 36 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer 37 %15 = icmp sgt <4 x i32> %wide.masked.load, %14 38 %16 = and <4 x i1> %12, %15 39 %17 = and <4 x i1> %16, %8 40 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> zeroinitializer, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %17) 41 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4 42 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 43 %19 = icmp ne i32 %18, 0 44 br i1 %19, label %vector.body, label %for.cond.cleanup 45 46 for.cond.cleanup: ; preds = %vector.body, %entry 47 ret void 48 } 49 50 define arm_aapcs_vfpcc void @different_vcpt_reaching_def(i32* nocapture %A, i32 %n, i32 %x) { 51 ; Intentionally left blank - see MIR sequence below. 52 entry: 53 unreachable 54 vector.ph: 55 unreachable 56 vector.body: 57 unreachable 58 for.cond.cleanup: 59 unreachable 60 } 61 62 define arm_aapcs_vfpcc void @different_vcpt_operand(i32* nocapture %A, i32 %n, i32 %x) { 63 ; Intentionally left blank - see MIR sequence below. 64 entry: 65 unreachable 66 vector.ph: 67 unreachable 68 vector.body: 69 unreachable 70 for.cond.cleanup: 71 unreachable 72 } 73 74 define arm_aapcs_vfpcc void @else_vcpt(i32* nocapture %data, i32 %N, i32 %T) { 75 entry: 76 %cmp9 = icmp sgt i32 %N, 0 77 %0 = add i32 %N, 3 78 %1 = lshr i32 %0, 2 79 %2 = shl nuw i32 %1, 2 80 %3 = add i32 %2, -4 81 %4 = lshr i32 %3, 2 82 %5 = add nuw nsw i32 %4, 1 83 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup 84 85 vector.ph: ; preds = %entry 86 %sub = sub nsw i32 0, %T 87 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 88 br label %vector.body 89 90 vector.body: ; preds = %vector.body, %vector.ph 91 %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %data, %vector.ph ] 92 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ] 93 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 94 %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>* 95 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 96 %9 = sub i32 %7, 4 97 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef) 98 %10 = insertelement <4 x i32> undef, i32 %T, i32 0 99 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer 100 %12 = icmp slt <4 x i32> %wide.masked.load, %11 101 %13 = insertelement <4 x i32> undef, i32 %sub, i32 0 102 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer 103 %15 = icmp sgt <4 x i32> %wide.masked.load, %14 104 %16 = or <4 x i1> %12, %15 105 %17 = and <4 x i1> %16, %8 106 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> zeroinitializer, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %17) 107 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4 108 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 109 %19 = icmp ne i32 %18, 0 110 br i1 %19, label %vector.body, label %for.cond.cleanup 111 112 for.cond.cleanup: ; preds = %vector.body, %entry 113 ret void 114 } 115 116 define arm_aapcs_vfpcc void @loop_invariant_vpt_operands(i32* nocapture %A, i32 %n, i32 %x) { 117 ; Intentionally left blank - see MIR sequence below. 118 entry: 119 unreachable 120 vector.ph: 121 unreachable 122 vector.body: 123 unreachable 124 for.cond.cleanup: 125 unreachable 126 } 127 128 define arm_aapcs_vfpcc void @vctp_before_vpt(i32* nocapture %A, i32 %n, i32 %x) { 129 ; Intentionally left blank - see MIR sequence below. 130 entry: 131 unreachable 132 vector.ph: 133 unreachable 134 vector.body: 135 unreachable 136 for.cond.cleanup: 137 unreachable 138 } 139 140 define arm_aapcs_vfpcc void @vpt_load_vctp_store(i32* nocapture %A, i32 %n, i32 %x) { 141 ; Intentionally left blank - see MIR sequence below. 142 entry: 143 unreachable 144 vector.ph: 145 unreachable 146 vector.body: 147 unreachable 148 for.cond.cleanup: 149 unreachable 150 } 151 152 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) 153 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 154 declare i32 @llvm.start.loop.iterations.i32(i32) 155 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 156 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 157... 158--- 159name: vpt_block 160alignment: 2 161exposesReturnsTwice: false 162legalized: false 163regBankSelected: false 164selected: false 165failedISel: false 166tracksRegLiveness: true 167hasWinCFI: false 168registers: [] 169liveins: 170 - { reg: '$r0', virtual-reg: '' } 171 - { reg: '$r1', virtual-reg: '' } 172 - { reg: '$r2', virtual-reg: '' } 173frameInfo: 174 isFrameAddressTaken: false 175 isReturnAddressTaken: false 176 hasStackMap: false 177 hasPatchPoint: false 178 stackSize: 8 179 offsetAdjustment: 0 180 maxAlignment: 4 181 adjustsStack: false 182 hasCalls: false 183 stackProtector: '' 184 maxCallFrameSize: 0 185 cvBytesOfCalleeSavedRegisters: 0 186 hasOpaqueSPAdjustment: false 187 hasVAStart: false 188 hasMustTailInVarArgFunc: false 189 localFrameSize: 0 190 savePoint: '' 191 restorePoint: '' 192fixedStack: [] 193stack: 194 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 195 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 196 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 197 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 198 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 199 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 200callSites: [] 201constants: [] 202machineFunctionInfo: {} 203body: | 204 ; CHECK-LABEL: name: vpt_block 205 ; CHECK: bb.0.entry: 206 ; CHECK: successors: %bb.1(0x80000000) 207 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 208 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 209 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 210 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 211 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 212 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 213 ; CHECK: t2IT 11, 8, implicit-def $itstate 214 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 215 ; CHECK: bb.1.vector.ph: 216 ; CHECK: successors: %bb.2(0x80000000) 217 ; CHECK: liveins: $r0, $r1, $r2 218 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 219 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 220 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 221 ; CHECK: bb.2.vector.body: 222 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 223 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 224 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg 225 ; CHECK: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr 226 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 227 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 228 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 229 ; CHECK: bb.3.for.cond.cleanup: 230 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 231 bb.0.entry: 232 successors: %bb.1(0x80000000) 233 liveins: $r0, $r1, $r2, $r7, $lr 234 235 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 236 frame-setup CFI_INSTRUCTION def_cfa_offset 8 237 frame-setup CFI_INSTRUCTION offset $lr, -4 238 frame-setup CFI_INSTRUCTION offset $r7, -8 239 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 240 t2IT 11, 8, implicit-def $itstate 241 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 242 243 bb.1.vector.ph: 244 successors: %bb.2(0x80000000) 245 liveins: $r0, $r1, $r2, $r7, $lr 246 247 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 248 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 249 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 250 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 251 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 252 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 253 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 254 $lr = t2DoLoopStart renamable $lr 255 256 bb.2.vector.body: 257 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 258 liveins: $lr, $q0, $r0, $r1, $r2, $r3 259 260 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 261 MVE_VPST 8, implicit $vpr 262 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 263 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 264 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 265 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 266 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 267 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 268 renamable $lr = t2LoopDec killed renamable $lr, 1 269 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 270 tB %bb.3, 14 /* CC::al */, $noreg 271 272 bb.3.for.cond.cleanup: 273 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 274... 275--- 276name: different_vcpt_reaching_def 277alignment: 2 278exposesReturnsTwice: false 279legalized: false 280regBankSelected: false 281selected: false 282failedISel: false 283tracksRegLiveness: true 284hasWinCFI: false 285registers: [] 286liveins: 287 - { reg: '$r0', virtual-reg: '' } 288 - { reg: '$r1', virtual-reg: '' } 289 - { reg: '$r2', virtual-reg: '' } 290frameInfo: 291 isFrameAddressTaken: false 292 isReturnAddressTaken: false 293 hasStackMap: false 294 hasPatchPoint: false 295 stackSize: 8 296 offsetAdjustment: 0 297 maxAlignment: 4 298 adjustsStack: false 299 hasCalls: false 300 stackProtector: '' 301 maxCallFrameSize: 0 302 cvBytesOfCalleeSavedRegisters: 0 303 hasOpaqueSPAdjustment: false 304 hasVAStart: false 305 hasMustTailInVarArgFunc: false 306 localFrameSize: 0 307 savePoint: '' 308 restorePoint: '' 309fixedStack: [] 310stack: 311 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 312 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 313 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 314 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 315 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 316 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 317callSites: [] 318constants: [] 319machineFunctionInfo: {} 320body: | 321 ; CHECK-LABEL: name: different_vcpt_reaching_def 322 ; CHECK: bb.0.entry: 323 ; CHECK: successors: %bb.1(0x80000000) 324 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 325 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 326 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 327 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 328 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 329 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 330 ; CHECK: t2IT 11, 8, implicit-def $itstate 331 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 332 ; CHECK: bb.1.vector.ph: 333 ; CHECK: successors: %bb.2(0x80000000) 334 ; CHECK: liveins: $r0, $r1, $r2 335 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 336 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 337 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 338 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 339 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 340 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 341 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 342 ; CHECK: $lr = t2DLS killed renamable $lr 343 ; CHECK: bb.2.vector.body: 344 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 345 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 346 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 347 ; CHECK: MVE_VPST 8, implicit $vpr 348 ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr 349 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 350 ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 351 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 352 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 353 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 354 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 355 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 356 ; CHECK: bb.3.for.cond.cleanup: 357 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 358 ; 359 ; Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main 360 ; VCTP's. 361 ; 362 bb.0.entry: 363 successors: %bb.1(0x80000000) 364 liveins: $r0, $r1, $r2, $r7, $lr 365 366 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 367 frame-setup CFI_INSTRUCTION def_cfa_offset 8 368 frame-setup CFI_INSTRUCTION offset $lr, -4 369 frame-setup CFI_INSTRUCTION offset $r7, -8 370 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 371 t2IT 11, 8, implicit-def $itstate 372 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 373 374 bb.1.vector.ph: 375 successors: %bb.2(0x80000000) 376 liveins: $r0, $r1, $r2, $r7, $lr 377 378 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 379 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 380 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 381 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 382 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 383 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 384 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 385 $lr = t2DoLoopStart renamable $lr 386 387 bb.2.vector.body: 388 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 389 liveins: $lr, $q0, $r0, $r1, $r2, $r3 390 391 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 392 MVE_VPST 8, implicit $vpr 393 renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr 394 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 395 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 396 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 397 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 398 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 399 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 400 renamable $lr = t2LoopDec killed renamable $lr, 1 401 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 402 tB %bb.3, 14 /* CC::al */, $noreg 403 404 bb.3.for.cond.cleanup: 405 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 406... 407--- 408name: different_vcpt_operand 409alignment: 2 410exposesReturnsTwice: false 411legalized: false 412regBankSelected: false 413selected: false 414failedISel: false 415tracksRegLiveness: true 416hasWinCFI: false 417registers: [] 418liveins: 419 - { reg: '$r0', virtual-reg: '' } 420 - { reg: '$r1', virtual-reg: '' } 421 - { reg: '$r2', virtual-reg: '' } 422frameInfo: 423 isFrameAddressTaken: false 424 isReturnAddressTaken: false 425 hasStackMap: false 426 hasPatchPoint: false 427 stackSize: 8 428 offsetAdjustment: 0 429 maxAlignment: 4 430 adjustsStack: false 431 hasCalls: false 432 stackProtector: '' 433 maxCallFrameSize: 0 434 cvBytesOfCalleeSavedRegisters: 0 435 hasOpaqueSPAdjustment: false 436 hasVAStart: false 437 hasMustTailInVarArgFunc: false 438 localFrameSize: 0 439 savePoint: '' 440 restorePoint: '' 441fixedStack: [] 442stack: 443 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 444 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 445 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 446 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 447 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 448 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 449callSites: [] 450constants: [] 451machineFunctionInfo: {} 452body: | 453 ; CHECK-LABEL: name: different_vcpt_operand 454 ; CHECK: bb.0.entry: 455 ; CHECK: successors: %bb.1(0x80000000) 456 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 457 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 458 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 459 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 460 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 461 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 462 ; CHECK: t2IT 11, 8, implicit-def $itstate 463 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 464 ; CHECK: bb.1.vector.ph: 465 ; CHECK: successors: %bb.2(0x80000000) 466 ; CHECK: liveins: $r0, $r1, $r2 467 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 468 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 469 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 470 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 471 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 472 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 473 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 474 ; CHECK: $lr = t2DLS killed renamable $lr 475 ; CHECK: bb.2.vector.body: 476 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 477 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 478 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 479 ; CHECK: MVE_VPST 8, implicit $vpr 480 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 481 ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 482 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 483 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 484 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 485 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 486 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 487 ; CHECK: bb.3.for.cond.cleanup: 488 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 489 ; 490 ; Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's. 491 ; 492 bb.0.entry: 493 successors: %bb.1(0x80000000) 494 liveins: $r0, $r1, $r2, $r7, $lr 495 496 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 497 frame-setup CFI_INSTRUCTION def_cfa_offset 8 498 frame-setup CFI_INSTRUCTION offset $lr, -4 499 frame-setup CFI_INSTRUCTION offset $r7, -8 500 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 501 t2IT 11, 8, implicit-def $itstate 502 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 503 504 bb.1.vector.ph: 505 successors: %bb.2(0x80000000) 506 liveins: $r0, $r1, $r2, $r7, $lr 507 508 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 509 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 510 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 511 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 512 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 513 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 514 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 515 $lr = t2DoLoopStart renamable $lr 516 517 bb.2.vector.body: 518 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 519 liveins: $lr, $q0, $r0, $r1, $r2, $r3 520 521 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 522 MVE_VPST 8, implicit $vpr 523 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 524 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 525 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 526 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 527 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 528 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 529 renamable $lr = t2LoopDec killed renamable $lr, 1 530 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 531 tB %bb.3, 14 /* CC::al */, $noreg 532 533 bb.3.for.cond.cleanup: 534 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 535... 536--- 537name: else_vcpt 538alignment: 2 539exposesReturnsTwice: false 540legalized: false 541regBankSelected: false 542selected: false 543failedISel: false 544tracksRegLiveness: true 545hasWinCFI: false 546registers: [] 547liveins: 548 - { reg: '$r0', virtual-reg: '' } 549 - { reg: '$r1', virtual-reg: '' } 550 - { reg: '$r2', virtual-reg: '' } 551frameInfo: 552 isFrameAddressTaken: false 553 isReturnAddressTaken: false 554 hasStackMap: false 555 hasPatchPoint: false 556 stackSize: 8 557 offsetAdjustment: 0 558 maxAlignment: 4 559 adjustsStack: false 560 hasCalls: false 561 stackProtector: '' 562 maxCallFrameSize: 0 563 cvBytesOfCalleeSavedRegisters: 0 564 hasOpaqueSPAdjustment: false 565 hasVAStart: false 566 hasMustTailInVarArgFunc: false 567 localFrameSize: 0 568 savePoint: '' 569 restorePoint: '' 570fixedStack: [] 571stack: 572 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 573 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 574 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 575 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 576 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 577 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 578callSites: [] 579constants: [] 580machineFunctionInfo: {} 581body: | 582 ; CHECK-LABEL: name: else_vcpt 583 ; CHECK: bb.0.entry: 584 ; CHECK: successors: %bb.1(0x80000000) 585 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 586 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 587 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 588 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 589 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 590 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 591 ; CHECK: t2IT 11, 8, implicit-def $itstate 592 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 593 ; CHECK: bb.1.vector.ph: 594 ; CHECK: successors: %bb.2(0x80000000) 595 ; CHECK: liveins: $r0, $r1, $r2 596 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 597 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 598 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 599 ; CHECK: bb.2.vector.body: 600 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 601 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 602 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg 603 ; CHECK: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr 604 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr 605 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr 606 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 607 ; CHECK: bb.3.for.cond.cleanup: 608 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 609 ; 610 ; Test including a else-predicated VCTP. 611 ; 612 bb.0.entry: 613 successors: %bb.1(0x80000000) 614 liveins: $r0, $r1, $r2, $r7, $lr 615 616 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 617 frame-setup CFI_INSTRUCTION def_cfa_offset 8 618 frame-setup CFI_INSTRUCTION offset $lr, -4 619 frame-setup CFI_INSTRUCTION offset $r7, -8 620 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 621 t2IT 11, 8, implicit-def $itstate 622 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 623 624 bb.1.vector.ph: 625 successors: %bb.2(0x80000000) 626 liveins: $r0, $r1, $r2, $r7, $lr 627 628 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 629 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 630 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 631 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 632 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 633 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 634 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 635 $lr = t2DoLoopStart renamable $lr 636 637 bb.2.vector.body: 638 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 639 liveins: $lr, $q0, $r0, $r1, $r2, $r3 640 641 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 642 MVE_VPST 8, implicit $vpr 643 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 644 MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr 645 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr 646 renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr 647 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr 648 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 649 renamable $lr = t2LoopDec killed renamable $lr, 1 650 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 651 tB %bb.3, 14 /* CC::al */, $noreg 652 653 bb.3.for.cond.cleanup: 654 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 655... 656--- 657name: loop_invariant_vpt_operands 658alignment: 2 659exposesReturnsTwice: false 660legalized: false 661regBankSelected: false 662selected: false 663failedISel: false 664tracksRegLiveness: true 665hasWinCFI: false 666registers: [] 667liveins: 668 - { reg: '$r0', virtual-reg: '' } 669 - { reg: '$r1', virtual-reg: '' } 670 - { reg: '$r2', virtual-reg: '' } 671frameInfo: 672 isFrameAddressTaken: false 673 isReturnAddressTaken: false 674 hasStackMap: false 675 hasPatchPoint: false 676 stackSize: 8 677 offsetAdjustment: 0 678 maxAlignment: 4 679 adjustsStack: false 680 hasCalls: false 681 stackProtector: '' 682 maxCallFrameSize: 0 683 cvBytesOfCalleeSavedRegisters: 0 684 hasOpaqueSPAdjustment: false 685 hasVAStart: false 686 hasMustTailInVarArgFunc: false 687 localFrameSize: 0 688 savePoint: '' 689 restorePoint: '' 690fixedStack: [] 691stack: 692 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 693 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 694 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 695 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 696 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 697 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 698callSites: [] 699constants: [] 700machineFunctionInfo: {} 701body: | 702 ; CHECK-LABEL: name: loop_invariant_vpt_operands 703 ; CHECK: bb.0.entry: 704 ; CHECK: successors: %bb.1(0x80000000) 705 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 706 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 707 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 708 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 709 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 710 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 711 ; CHECK: t2IT 11, 8, implicit-def $itstate 712 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 713 ; CHECK: bb.1.vector.ph: 714 ; CHECK: successors: %bb.2(0x80000000) 715 ; CHECK: liveins: $r0, $r1, $r2 716 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 717 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 718 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 719 ; CHECK: bb.2.vector.body: 720 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 721 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 722 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg 723 ; CHECK: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr 724 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 725 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 726 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 727 ; CHECK: bb.3.for.cond.cleanup: 728 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 729 bb.0.entry: 730 successors: %bb.1(0x80000000) 731 liveins: $r0, $r1, $r2, $r7, $lr 732 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 733 frame-setup CFI_INSTRUCTION def_cfa_offset 8 734 frame-setup CFI_INSTRUCTION offset $lr, -4 735 frame-setup CFI_INSTRUCTION offset $r7, -8 736 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 737 t2IT 11, 8, implicit-def $itstate 738 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 739 740 bb.1.vector.ph: 741 successors: %bb.2(0x80000000) 742 liveins: $r0, $r1, $r2, $r7, $lr 743 744 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 745 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 746 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 747 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 748 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 749 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 750 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 751 $lr = t2DoLoopStart renamable $lr 752 753 bb.2.vector.body: 754 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 755 liveins: $lr, $q0, $r0, $r1, $r2, $r3 756 757 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 758 MVE_VPST 8, implicit $vpr 759 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 760 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr 761 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 762 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 763 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 764 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 765 renamable $lr = t2LoopDec killed renamable $lr, 1 766 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 767 tB %bb.3, 14 /* CC::al */, $noreg 768 769 bb.3.for.cond.cleanup: 770 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 771... 772--- 773name: vctp_before_vpt 774alignment: 2 775exposesReturnsTwice: false 776legalized: false 777regBankSelected: false 778selected: false 779failedISel: false 780tracksRegLiveness: true 781hasWinCFI: false 782registers: [] 783liveins: 784 - { reg: '$r0', virtual-reg: '' } 785 - { reg: '$r1', virtual-reg: '' } 786 - { reg: '$r2', virtual-reg: '' } 787frameInfo: 788 isFrameAddressTaken: false 789 isReturnAddressTaken: false 790 hasStackMap: false 791 hasPatchPoint: false 792 stackSize: 8 793 offsetAdjustment: 0 794 maxAlignment: 4 795 adjustsStack: false 796 hasCalls: false 797 stackProtector: '' 798 maxCallFrameSize: 0 799 cvBytesOfCalleeSavedRegisters: 0 800 hasOpaqueSPAdjustment: false 801 hasVAStart: false 802 hasMustTailInVarArgFunc: false 803 localFrameSize: 0 804 savePoint: '' 805 restorePoint: '' 806fixedStack: [] 807stack: 808 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 809 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 810 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 811 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 812 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 813 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 814callSites: [] 815constants: [] 816machineFunctionInfo: {} 817body: | 818 ; CHECK-LABEL: name: vctp_before_vpt 819 ; CHECK: bb.0.entry: 820 ; CHECK: successors: %bb.1(0x80000000) 821 ; CHECK: liveins: $lr, $r1, $r2, $r7 822 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 823 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 824 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 825 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 826 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 827 ; CHECK: t2IT 11, 8, implicit-def $itstate 828 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 829 ; CHECK: bb.1.vector.ph: 830 ; CHECK: successors: %bb.2(0x80000000) 831 ; CHECK: liveins: $r1, $r2 832 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 833 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 834 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 835 ; CHECK: bb.2.vector.body: 836 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 837 ; CHECK: liveins: $lr, $q0, $r2, $r3 838 ; CHECK: MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 8, implicit-def $vpr 839 ; CHECK: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr 840 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 841 ; CHECK: bb.3.for.cond.cleanup: 842 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 843 bb.0.entry: 844 successors: %bb.1(0x80000000) 845 liveins: $r0, $r1, $r2, $r7, $lr 846 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 847 frame-setup CFI_INSTRUCTION def_cfa_offset 8 848 frame-setup CFI_INSTRUCTION offset $lr, -4 849 frame-setup CFI_INSTRUCTION offset $r7, -8 850 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 851 t2IT 11, 8, implicit-def $itstate 852 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 853 854 bb.1.vector.ph: 855 successors: %bb.2(0x80000000) 856 liveins: $r0, $r1, $r2, $r7, $lr 857 858 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 859 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 860 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 861 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 862 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 863 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 864 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 865 $lr = t2DoLoopStart renamable $lr 866 867 bb.2.vector.body: 868 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 869 liveins: $lr, $q0, $r0, $r1, $r2, $r3 870 871 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 8, implicit-def $vpr 872 renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr 873 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 874 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 875 renamable $lr = t2LoopDec killed renamable $lr, 1 876 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 877 tB %bb.3, 14 /* CC::al */, $noreg 878 879 bb.3.for.cond.cleanup: 880 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 881... 882--- 883name: vpt_load_vctp_store 884alignment: 2 885exposesReturnsTwice: false 886legalized: false 887regBankSelected: false 888selected: false 889failedISel: false 890tracksRegLiveness: true 891hasWinCFI: false 892registers: [] 893liveins: 894 - { reg: '$r0', virtual-reg: '' } 895 - { reg: '$r1', virtual-reg: '' } 896 - { reg: '$r2', virtual-reg: '' } 897frameInfo: 898 isFrameAddressTaken: false 899 isReturnAddressTaken: false 900 hasStackMap: false 901 hasPatchPoint: false 902 stackSize: 8 903 offsetAdjustment: 0 904 maxAlignment: 4 905 adjustsStack: false 906 hasCalls: false 907 stackProtector: '' 908 maxCallFrameSize: 0 909 cvBytesOfCalleeSavedRegisters: 0 910 hasOpaqueSPAdjustment: false 911 hasVAStart: false 912 hasMustTailInVarArgFunc: false 913 localFrameSize: 0 914 savePoint: '' 915 restorePoint: '' 916fixedStack: [] 917stack: 918 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 919 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 920 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 921 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 922 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 923 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 924callSites: [] 925constants: [] 926machineFunctionInfo: {} 927body: | 928 ; CHECK-LABEL: name: vpt_load_vctp_store 929 ; CHECK: bb.0.entry: 930 ; CHECK: successors: %bb.1(0x80000000) 931 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 932 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 933 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 934 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 935 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 936 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 937 ; CHECK: t2IT 11, 8, implicit-def $itstate 938 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 939 ; CHECK: bb.1.vector.ph: 940 ; CHECK: successors: %bb.2(0x80000000) 941 ; CHECK: liveins: $r0, $r1, $r2 942 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 943 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 944 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 945 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 946 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 947 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 948 ; CHECK: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 949 ; CHECK: $lr = t2DLS killed renamable $lr 950 ; CHECK: bb.2.vector.body: 951 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 952 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2 953 ; CHECK: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr 954 ; CHECK: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr 955 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr 956 ; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr 957 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 958 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 959 ; CHECK: bb.3.for.cond.cleanup: 960 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 961 ; 962 ; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP. 963 ; 964 bb.0.entry: 965 successors: %bb.1(0x80000000) 966 liveins: $r0, $r1, $r2, $r7, $lr 967 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 968 frame-setup CFI_INSTRUCTION def_cfa_offset 8 969 frame-setup CFI_INSTRUCTION offset $lr, -4 970 frame-setup CFI_INSTRUCTION offset $r7, -8 971 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 972 t2IT 11, 8, implicit-def $itstate 973 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 974 975 bb.1.vector.ph: 976 successors: %bb.2(0x80000000) 977 liveins: $r0, $r1, $r2, $r7, $lr 978 979 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 980 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 981 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 982 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 983 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 984 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 985 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 986 $lr = t2DoLoopStart renamable $lr 987 988 bb.2.vector.body: 989 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 990 liveins: $lr, $q0, $r0, $r1, $r2, $r3 991 992 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 2, implicit-def $vpr 993 renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr 994 renamable $vpr = MVE_VCTP32 renamable $r1, 1, $vpr 995 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, $vpr 996 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 997 renamable $lr = t2LoopDec killed renamable $lr, 1 998 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 999 tB %bb.3, 14 /* CC::al */, $noreg 1000 1001 bb.3.for.cond.cleanup: 1002 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1003... 1004