1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
3
4# TODO: Remove the lr = tMOVr which actually makes the WLS def dead!
5
6--- |
7  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
8  target triple = "thumbv8.1m.main"
9
10  define dso_local arm_aapcscc void @copy(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {
11  entry:
12    %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
13    br i1 %0, label %while.body.preheader, label %while.end
14
15  while.body.preheader:                             ; preds = %entry
16    %scevgep = getelementptr i16, i16* %a, i32 -1
17    %scevgep3 = getelementptr i16, i16* %b, i32 -1
18    br label %while.body
19
20  while.body:                                       ; preds = %while.body, %while.body.preheader
21    %lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]
22    %lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]
23    %1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ]
24    %scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1
25    %scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1
26    %2 = load i16, i16* %scevgep4, align 2
27    store i16 %2, i16* %scevgep7, align 2
28    %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
29    %4 = icmp ne i32 %3, 0
30    %scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1
31    %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1
32    br i1 %4, label %while.body, label %while.end
33
34  while.end:                                        ; preds = %while.body, %entry
35    ret void
36  }
37
38  declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
39  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
40
41  attributes #0 = { noduplicate nounwind }
42  attributes #1 = { nounwind }
43
44...
45---
46name:            copy
47alignment:       2
48exposesReturnsTwice: false
49legalized:       false
50regBankSelected: false
51selected:        false
52failedISel:      false
53tracksRegLiveness: true
54hasWinCFI:       false
55registers:       []
56liveins:
57  - { reg: '$r0', virtual-reg: '' }
58  - { reg: '$r1', virtual-reg: '' }
59  - { reg: '$r2', virtual-reg: '' }
60frameInfo:
61  isFrameAddressTaken: false
62  isReturnAddressTaken: false
63  hasStackMap:     false
64  hasPatchPoint:   false
65  stackSize:       8
66  offsetAdjustment: 0
67  maxAlignment:    4
68  adjustsStack:    false
69  hasCalls:        false
70  stackProtector:  ''
71  maxCallFrameSize: 0
72  cvBytesOfCalleeSavedRegisters: 0
73  hasOpaqueSPAdjustment: false
74  hasVAStart:      false
75  hasMustTailInVarArgFunc: false
76  localFrameSize:  0
77  savePoint:       ''
78  restorePoint:    ''
79fixedStack:      []
80stack:
81  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
82      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
83      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
84  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
85      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
86      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
87callSites:       []
88constants:       []
89machineFunctionInfo: {}
90body:             |
91  ; CHECK-LABEL: name: copy
92  ; CHECK: bb.0.entry:
93  ; CHECK:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
94  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
95  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
96  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
97  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
98  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
99  ; CHECK:   dead $lr = t2WLS $r2, %bb.3
100  ; CHECK: bb.1.while.body.preheader:
101  ; CHECK:   successors: %bb.2(0x80000000)
102  ; CHECK:   liveins: $r0, $r1, $r2
103  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg
104  ; CHECK:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg
105  ; CHECK:   $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
106  ; CHECK: bb.2.while.body:
107  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
108  ; CHECK:   liveins: $lr, $r0, $r1
109  ; CHECK:   renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.scevgep4)
110  ; CHECK:   early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store 2 into %ir.scevgep7)
111  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
112  ; CHECK: bb.3.while.end:
113  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
114  bb.0.entry:
115    successors: %bb.1(0x40000000), %bb.3(0x40000000)
116    liveins: $r0, $r1, $r2, $r7, $lr
117
118    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
119    frame-setup CFI_INSTRUCTION def_cfa_offset 8
120    frame-setup CFI_INSTRUCTION offset $lr, -4
121    frame-setup CFI_INSTRUCTION offset $r7, -8
122    t2WhileLoopStart $r2, %bb.3, implicit-def dead $cpsr
123    tB %bb.1, 14, $noreg
124
125  bb.1.while.body.preheader:
126    successors: %bb.2(0x80000000)
127    liveins: $r0, $r1, $r2
128
129    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
130    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
131    $lr = tMOVr killed $r2, 14, $noreg
132
133  bb.2.while.body:
134    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
135    liveins: $lr, $r0, $r1
136
137    renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)
138    early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)
139    renamable $lr = t2LoopDec killed renamable $lr, 1
140    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
141    tB %bb.3, 14, $noreg
142
143  bb.3.while.end:
144    tPOP_RET 14, $noreg, def $r7, def $pc
145
146...
147