1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4# I think this should be equivalent, but the calculation in the middle block
5# is too complex to process for now.
6
7--- |
8  define dso_local i32 @wrong_vctp_liveout(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
9  entry:
10    %cmp9 = icmp eq i32 %N, 0
11    %tmp = add i32 %N, 3
12    %tmp1 = lshr i32 %tmp, 2
13    %tmp2 = shl nuw i32 %tmp1, 2
14    %tmp3 = add i32 %tmp2, -4
15    %tmp4 = lshr i32 %tmp3, 2
16    %tmp5 = add nuw nsw i32 %tmp4, 1
17    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
18
19  vector.ph:                                        ; preds = %entry
20    %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)
21    br label %vector.body
22
23  vector.body:                                      ; preds = %vector.body, %vector.ph
24    %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
25    %lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ]
26    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
27    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]
28    %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]
29    %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>*
30    %lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>*
31    %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)
32    %tmp9 = sub i32 %tmp7, 4
33    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
34    %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
35    %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
36    %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>
37    %tmp12 = mul nsw <4 x i32> %tmp11, %tmp10
38    %tmp13 = add <4 x i32> %tmp12, %vec.phi
39    %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
40    %scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4
41    %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
42    %tmp15 = icmp ne i32 %tmp14, 0
43    %lsr.iv.next = add nsw i32 %lsr.iv1, -1
44    br i1 %tmp15, label %vector.body, label %middle.block
45
46  middle.block:                                     ; preds = %vector.body
47    %0 = add i32 %tmp9, 4
48    %insert.idx = insertelement <4 x i32> undef, i32 %0, i32 0
49    %idx.splat = shufflevector <4 x i32> %insert.idx, <4 x i32> undef, <4 x i32> zeroinitializer
50    %n.minusone = add i32 %N, -1
51    %insert.n = insertelement <4 x i32> undef, i32 %n.minusone, i32 0
52    %n.splat = shufflevector <4 x i32> %insert.n, <4 x i32> undef, <4 x i32> zeroinitializer
53    %tmp16 = icmp ult <4 x i32> %idx.splat, %n.splat
54    %tmp17 = select <4 x i1> %tmp16, <4 x i32> %tmp13, <4 x i32> %vec.phi
55    %tmp18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp17)
56    br label %for.cond.cleanup
57
58  for.cond.cleanup:                                 ; preds = %middle.block, %entry
59    %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp18, %middle.block ]
60    ret i32 %res.0.lcssa
61  }
62  declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
63  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
64  declare i32 @llvm.start.loop.iterations.i32(i32) #3
65  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
66  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
67
68...
69---
70name:            wrong_vctp_liveout
71alignment:       2
72exposesReturnsTwice: false
73legalized:       false
74regBankSelected: false
75selected:        false
76failedISel:      false
77tracksRegLiveness: true
78hasWinCFI:       false
79registers:       []
80liveins:
81  - { reg: '$r0', virtual-reg: '' }
82  - { reg: '$r1', virtual-reg: '' }
83  - { reg: '$r2', virtual-reg: '' }
84frameInfo:
85  isFrameAddressTaken: false
86  isReturnAddressTaken: false
87  hasStackMap:     false
88  hasPatchPoint:   false
89  stackSize:       8
90  offsetAdjustment: 0
91  maxAlignment:    4
92  adjustsStack:    false
93  hasCalls:        false
94  stackProtector:  ''
95  maxCallFrameSize: 0
96  cvBytesOfCalleeSavedRegisters: 0
97  hasOpaqueSPAdjustment: false
98  hasVAStart:      false
99  hasMustTailInVarArgFunc: false
100  localFrameSize:  0
101  savePoint:       ''
102  restorePoint:    ''
103fixedStack:      []
104stack:
105  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
106      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
107      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
108  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
109      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
110      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
111callSites:       []
112constants:       []
113machineFunctionInfo: {}
114body:             |
115  ; CHECK-LABEL: name: wrong_vctp_liveout
116  ; CHECK: bb.0.entry:
117  ; CHECK:   successors: %bb.1(0x80000000)
118  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
119  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
120  ; CHECK:   t2IT 0, 4, implicit-def $itstate
121  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
122  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
123  ; CHECK: bb.1.vector.ph:
124  ; CHECK:   successors: %bb.2(0x80000000)
125  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
126  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
127  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
128  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
129  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
130  ; CHECK:   renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
131  ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
132  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
133  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
134  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
135  ; CHECK:   renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
136  ; CHECK:   dead $lr = t2DLS renamable $r3
137  ; CHECK:   $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg
138  ; CHECK:   $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
139  ; CHECK: bb.2.vector.body:
140  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
141  ; CHECK:   liveins: $q1, $r0, $r1, $r2, $r3, $r12
142  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
143  ; CHECK:   $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
144  ; CHECK:   MVE_VPST 4, implicit $vpr
145  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
146  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
147  ; CHECK:   $lr = tMOVr $r12, 14 /* CC::al */, $noreg
148  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
149  ; CHECK:   renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
150  ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
151  ; CHECK:   renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
152  ; CHECK:   dead $lr = t2LEUpdate killed renamable $lr, %bb.2
153  ; CHECK: bb.3.middle.block:
154  ; CHECK:   liveins: $q0, $q1, $r2, $r3
155  ; CHECK:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14 /* CC::al */, $noreg
156  ; CHECK:   renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, undef renamable $q2
157  ; CHECK:   renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
158  ; CHECK:   renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg
159  ; CHECK:   renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
160  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
161  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
162  bb.0.entry:
163    successors: %bb.1(0x80000000)
164    liveins: $r0, $r1, $r2, $lr, $r7
165
166    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
167    t2IT 0, 4, implicit-def $itstate
168    renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
169    tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
170
171  bb.1.vector.ph:
172    successors: %bb.2(0x80000000)
173    liveins: $r0, $r1, $r2, $lr, $r7
174
175    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
176    frame-setup CFI_INSTRUCTION def_cfa_offset 8
177    frame-setup CFI_INSTRUCTION offset $lr, -4
178    frame-setup CFI_INSTRUCTION offset $r7, -8
179    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
180    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
181    renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
182    renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
183    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
184    renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
185    $lr = t2DoLoopStart renamable $r3
186    $r12 = tMOVr killed $r3, 14, $noreg
187    $r3 = tMOVr $r2, 14, $noreg
188
189  bb.2.vector.body:
190    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
191    liveins: $q1, $r0, $r1, $r2, $r3, $r12
192
193    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
194    $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0
195    MVE_VPST 4, implicit $vpr
196    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
197    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
198    $lr = tMOVr $r12, 14, $noreg
199    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
200    renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg
201    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
202    renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
203    renamable $lr = t2LoopDec killed renamable $lr, 1
204    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
205    tB %bb.3, 14, $noreg
206
207  bb.3.middle.block:
208    liveins: $q0, $q1, $r2, $r3
209
210    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14, $noreg
211    renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, undef renamable $q2
212    renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14, $noreg
213    renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg
214    renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
215    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
216    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
217
218...
219