1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4# The VCTP uses r2, which is redefined in the loop.
5
6--- |
7  define dso_local i32 @wrong_vctp_liveout(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
8  entry:
9    %cmp9 = icmp eq i32 %N, 0
10    %0 = add i32 %N, 3
11    %1 = lshr i32 %0, 2
12    %2 = shl nuw i32 %1, 2
13    %3 = add i32 %2, -4
14    %4 = lshr i32 %3, 2
15    %5 = add nuw nsw i32 %4, 1
16    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
17
18  vector.ph:                                        ; preds = %entry
19    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
20    br label %vector.body
21
22  vector.body:                                      ; preds = %vector.body, %vector.ph
23    %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
24    %lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ]
25    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
26    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
27    %6 = phi i32 [ %N, %vector.ph ], [ %8, %vector.body ]
28    %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>*
29    %lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>*
30    %7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6)
31    %8 = sub i32 %6, 4
32    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %7, <4 x i16> undef)
33    %9 = sext <4 x i16> %wide.masked.load to <4 x i32>
34    %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %7, <4 x i16> undef)
35    %10 = sext <4 x i16> %wide.masked.load14 to <4 x i32>
36    %11 = mul nsw <4 x i32> %10, %9
37    %12 = add <4 x i32> %11, %vec.phi
38    %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
39    %scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4
40    %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
41    %14 = icmp ne i32 %13, 0
42    %lsr.iv.next = add nsw i32 %lsr.iv1, -1
43    br i1 %14, label %vector.body, label %middle.block
44
45  middle.block:                                     ; preds = %vector.body
46    %15 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %8)
47    %16 = select <4 x i1> %15, <4 x i32> %12, <4 x i32> %vec.phi
48    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %16)
49    br label %for.cond.cleanup
50
51  for.cond.cleanup:                                 ; preds = %middle.block, %entry
52    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
53    ret i32 %res.0.lcssa
54  }
55  declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
56  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
57  declare i32 @llvm.start.loop.iterations.i32(i32) #3
58  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
59  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
60...
61---
62name:            wrong_vctp_liveout
63alignment:       2
64exposesReturnsTwice: false
65legalized:       false
66regBankSelected: false
67selected:        false
68failedISel:      false
69tracksRegLiveness: true
70hasWinCFI:       false
71registers:       []
72liveins:
73  - { reg: '$r0', virtual-reg: '' }
74  - { reg: '$r1', virtual-reg: '' }
75  - { reg: '$r2', virtual-reg: '' }
76frameInfo:
77  isFrameAddressTaken: false
78  isReturnAddressTaken: false
79  hasStackMap:     false
80  hasPatchPoint:   false
81  stackSize:       8
82  offsetAdjustment: 0
83  maxAlignment:    4
84  adjustsStack:    false
85  hasCalls:        false
86  stackProtector:  ''
87  maxCallFrameSize: 0
88  cvBytesOfCalleeSavedRegisters: 0
89  hasOpaqueSPAdjustment: false
90  hasVAStart:      false
91  hasMustTailInVarArgFunc: false
92  localFrameSize:  0
93  savePoint:       ''
94  restorePoint:    ''
95fixedStack:      []
96stack:
97  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
98      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
99      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
100  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
101      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
102      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
103callSites:       []
104constants:       []
105machineFunctionInfo: {}
106body:             |
107  ; CHECK-LABEL: name: wrong_vctp_liveout
108  ; CHECK: bb.0.entry:
109  ; CHECK:   successors: %bb.1(0x80000000)
110  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
111  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
112  ; CHECK:   t2IT 0, 4, implicit-def $itstate
113  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
114  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
115  ; CHECK: bb.1.vector.ph:
116  ; CHECK:   successors: %bb.2(0x80000000)
117  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
118  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
119  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
120  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
121  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
122  ; CHECK:   renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
123  ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
124  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
125  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
126  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
127  ; CHECK:   renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
128  ; CHECK:   dead $lr = t2DLS renamable $r12
129  ; CHECK:   $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
130  ; CHECK: bb.2.vector.body:
131  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
132  ; CHECK:   liveins: $q1, $r0, $r1, $r2, $r3
133  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
134  ; CHECK:   $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
135  ; CHECK:   MVE_VPST 4, implicit $vpr
136  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
137  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
138  ; CHECK:   $lr = tMOVr $r3, 14 /* CC::al */, $noreg
139  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
140  ; CHECK:   renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
141  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
142  ; CHECK:   renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
143  ; CHECK:   dead $lr = t2LEUpdate killed renamable $lr, %bb.2
144  ; CHECK: bb.3.middle.block:
145  ; CHECK:   liveins: $q0, $q1, $r2
146  ; CHECK:   renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg
147  ; CHECK:   renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
148  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
149  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
150  bb.0.entry:
151    successors: %bb.1(0x80000000)
152    liveins: $r0, $r1, $r2, $lr, $r7
153
154    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
155    t2IT 0, 4, implicit-def $itstate
156    renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
157    tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
158
159  bb.1.vector.ph:
160    successors: %bb.2(0x80000000)
161    liveins: $r0, $r1, $r2, $lr, $r7
162
163    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
164    frame-setup CFI_INSTRUCTION def_cfa_offset 8
165    frame-setup CFI_INSTRUCTION offset $lr, -4
166    frame-setup CFI_INSTRUCTION offset $r7, -8
167    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
168    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
169    renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
170    renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
171    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
172    renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
173    $lr = t2DoLoopStart renamable $r12
174    $r3 = tMOVr killed $r12, 14, $noreg
175
176  bb.2.vector.body:
177    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
178    liveins: $q1, $r0, $r1, $r2, $r3
179
180    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
181    $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0
182    MVE_VPST 4, implicit $vpr
183    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
184    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
185    $lr = tMOVr $r3, 14, $noreg
186    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
187    renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
188    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
189    renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
190    renamable $lr = t2LoopDec killed renamable $lr, 1
191    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
192    tB %bb.3, 14, $noreg
193
194  bb.3.middle.block:
195    liveins: $q0, $q1, $r2
196
197    renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg
198    renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
199    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
200    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
201
202...
203