1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <16 x i8> @and_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
5; CHECK-LABEL: and_int8_t:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vand q0, q0, q1
8; CHECK-NEXT:    bx lr
9entry:
10  %0 = and <16 x i8> %src1, %src2
11  ret <16 x i8> %0
12}
13
14define arm_aapcs_vfpcc <8 x i16> @and_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
15; CHECK-LABEL: and_int16_t:
16; CHECK:       @ %bb.0: @ %entry
17; CHECK-NEXT:    vand q0, q0, q1
18; CHECK-NEXT:    bx lr
19entry:
20  %0 = and <8 x i16> %src1, %src2
21  ret <8 x i16> %0
22}
23
24define arm_aapcs_vfpcc <4 x i32> @and_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
25; CHECK-LABEL: and_int32_t:
26; CHECK:       @ %bb.0: @ %entry
27; CHECK-NEXT:    vand q0, q0, q1
28; CHECK-NEXT:    bx lr
29entry:
30  %0 = and <4 x i32> %src1, %src2
31  ret <4 x i32> %0
32}
33
34define arm_aapcs_vfpcc <2 x i64> @and_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
35; CHECK-LABEL: and_int64_t:
36; CHECK:       @ %bb.0: @ %entry
37; CHECK-NEXT:    vand q0, q0, q1
38; CHECK-NEXT:    bx lr
39entry:
40  %0 = and <2 x i64> %src1, %src2
41  ret <2 x i64> %0
42}
43
44
45define arm_aapcs_vfpcc <16 x i8> @or_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
46; CHECK-LABEL: or_int8_t:
47; CHECK:       @ %bb.0: @ %entry
48; CHECK-NEXT:    vorr q0, q0, q1
49; CHECK-NEXT:    bx lr
50entry:
51  %0 = or <16 x i8> %src1, %src2
52  ret <16 x i8> %0
53}
54
55define arm_aapcs_vfpcc <8 x i16> @or_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
56; CHECK-LABEL: or_int16_t:
57; CHECK:       @ %bb.0: @ %entry
58; CHECK-NEXT:    vorr q0, q0, q1
59; CHECK-NEXT:    bx lr
60entry:
61  %0 = or <8 x i16> %src1, %src2
62  ret <8 x i16> %0
63}
64
65define arm_aapcs_vfpcc <4 x i32> @or_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
66; CHECK-LABEL: or_int32_t:
67; CHECK:       @ %bb.0: @ %entry
68; CHECK-NEXT:    vorr q0, q0, q1
69; CHECK-NEXT:    bx lr
70entry:
71  %0 = or <4 x i32> %src1, %src2
72  ret <4 x i32> %0
73}
74
75define arm_aapcs_vfpcc <2 x i64> @or_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
76; CHECK-LABEL: or_int64_t:
77; CHECK:       @ %bb.0: @ %entry
78; CHECK-NEXT:    vorr q0, q0, q1
79; CHECK-NEXT:    bx lr
80entry:
81  %0 = or <2 x i64> %src1, %src2
82  ret <2 x i64> %0
83}
84
85
86define arm_aapcs_vfpcc <16 x i8> @xor_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
87; CHECK-LABEL: xor_int8_t:
88; CHECK:       @ %bb.0: @ %entry
89; CHECK-NEXT:    veor q0, q0, q1
90; CHECK-NEXT:    bx lr
91entry:
92  %0 = xor <16 x i8> %src1, %src2
93  ret <16 x i8> %0
94}
95
96define arm_aapcs_vfpcc <8 x i16> @xor_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
97; CHECK-LABEL: xor_int16_t:
98; CHECK:       @ %bb.0: @ %entry
99; CHECK-NEXT:    veor q0, q0, q1
100; CHECK-NEXT:    bx lr
101entry:
102  %0 = xor <8 x i16> %src1, %src2
103  ret <8 x i16> %0
104}
105
106define arm_aapcs_vfpcc <4 x i32> @xor_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
107; CHECK-LABEL: xor_int32_t:
108; CHECK:       @ %bb.0: @ %entry
109; CHECK-NEXT:    veor q0, q0, q1
110; CHECK-NEXT:    bx lr
111entry:
112  %0 = xor <4 x i32> %src1, %src2
113  ret <4 x i32> %0
114}
115
116define arm_aapcs_vfpcc <2 x i64> @xor_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
117; CHECK-LABEL: xor_int64_t:
118; CHECK:       @ %bb.0: @ %entry
119; CHECK-NEXT:    veor q0, q0, q1
120; CHECK-NEXT:    bx lr
121entry:
122  %0 = xor <2 x i64> %src1, %src2
123  ret <2 x i64> %0
124}
125
126define arm_aapcs_vfpcc <16 x i8> @v_mvn_i8(<16 x i8> %src) {
127; CHECK-LABEL: v_mvn_i8:
128; CHECK:       @ %bb.0: @ %entry
129; CHECK-NEXT:    vmvn q0, q0
130; CHECK-NEXT:    bx lr
131entry:
132  %0 = xor <16 x i8> %src, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
133  ret <16 x i8> %0
134}
135
136define arm_aapcs_vfpcc <8 x i16> @v_mvn_i16(<8 x i16> %src) {
137; CHECK-LABEL: v_mvn_i16:
138; CHECK:       @ %bb.0: @ %entry
139; CHECK-NEXT:    vmvn q0, q0
140; CHECK-NEXT:    bx lr
141entry:
142  %0 = xor <8 x i16> %src, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
143  ret <8 x i16> %0
144}
145
146define arm_aapcs_vfpcc <4 x i32> @v_mvn_i32(<4 x i32> %src) {
147; CHECK-LABEL: v_mvn_i32:
148; CHECK:       @ %bb.0: @ %entry
149; CHECK-NEXT:    vmvn q0, q0
150; CHECK-NEXT:    bx lr
151entry:
152  %0 = xor <4 x i32> %src, <i32 -1, i32 -1, i32 -1, i32 -1>
153  ret <4 x i32> %0
154}
155
156define arm_aapcs_vfpcc <2 x i64> @v_mvn_i64(<2 x i64> %src) {
157; CHECK-LABEL: v_mvn_i64:
158; CHECK:       @ %bb.0: @ %entry
159; CHECK-NEXT:    vmvn q0, q0
160; CHECK-NEXT:    bx lr
161entry:
162  %0 = xor <2 x i64> %src, <i64 -1, i64 -1>
163  ret <2 x i64> %0
164}
165
166
167define arm_aapcs_vfpcc <16 x i8> @v_bic_i8(<16 x i8> %src1, <16 x i8> %src2) {
168; CHECK-LABEL: v_bic_i8:
169; CHECK:       @ %bb.0: @ %entry
170; CHECK-NEXT:    vbic q0, q1, q0
171; CHECK-NEXT:    bx lr
172entry:
173  %0 = xor <16 x i8> %src1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
174  %1 = and <16 x i8> %src2, %0
175  ret <16 x i8> %1
176}
177
178define arm_aapcs_vfpcc <8 x i16> @v_bic_i16(<8 x i16> %src1, <8 x i16> %src2) {
179; CHECK-LABEL: v_bic_i16:
180; CHECK:       @ %bb.0: @ %entry
181; CHECK-NEXT:    vbic q0, q1, q0
182; CHECK-NEXT:    bx lr
183entry:
184  %0 = xor <8 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
185  %1 = and <8 x i16> %src2, %0
186  ret <8 x i16> %1
187}
188
189define arm_aapcs_vfpcc <4 x i32> @v_bic_i32(<4 x i32> %src1, <4 x i32> %src2) {
190; CHECK-LABEL: v_bic_i32:
191; CHECK:       @ %bb.0: @ %entry
192; CHECK-NEXT:    vbic q0, q1, q0
193; CHECK-NEXT:    bx lr
194entry:
195  %0 = xor <4 x i32> %src1, <i32 -1, i32 -1, i32 -1, i32 -1>
196  %1 = and <4 x i32> %src2, %0
197  ret <4 x i32> %1
198}
199
200define arm_aapcs_vfpcc <2 x i64> @v_bic_i64(<2 x i64> %src1, <2 x i64> %src2) {
201; CHECK-LABEL: v_bic_i64:
202; CHECK:       @ %bb.0: @ %entry
203; CHECK-NEXT:    vbic q0, q1, q0
204; CHECK-NEXT:    bx lr
205entry:
206  %0 = xor <2 x i64> %src1, <i64 -1, i64 -1>
207  %1 = and <2 x i64> %src2, %0
208  ret <2 x i64> %1
209}
210
211
212define arm_aapcs_vfpcc <16 x i8> @v_or_i8(<16 x i8> %src1, <16 x i8> %src2) {
213; CHECK-LABEL: v_or_i8:
214; CHECK:       @ %bb.0: @ %entry
215; CHECK-NEXT:    vorn q0, q1, q0
216; CHECK-NEXT:    bx lr
217entry:
218  %0 = xor <16 x i8> %src1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
219  %1 = or <16 x i8> %src2, %0
220  ret <16 x i8> %1
221}
222
223define arm_aapcs_vfpcc <8 x i16> @v_or_i16(<8 x i16> %src1, <8 x i16> %src2) {
224; CHECK-LABEL: v_or_i16:
225; CHECK:       @ %bb.0: @ %entry
226; CHECK-NEXT:    vorn q0, q1, q0
227; CHECK-NEXT:    bx lr
228entry:
229  %0 = xor <8 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
230  %1 = or <8 x i16> %src2, %0
231  ret <8 x i16> %1
232}
233
234define arm_aapcs_vfpcc <4 x i32> @v_or_i32(<4 x i32> %src1, <4 x i32> %src2) {
235; CHECK-LABEL: v_or_i32:
236; CHECK:       @ %bb.0: @ %entry
237; CHECK-NEXT:    vorn q0, q1, q0
238; CHECK-NEXT:    bx lr
239entry:
240  %0 = xor <4 x i32> %src1, <i32 -1, i32 -1, i32 -1, i32 -1>
241  %1 = or <4 x i32> %src2, %0
242  ret <4 x i32> %1
243}
244
245define arm_aapcs_vfpcc <2 x i64> @v_or_i64(<2 x i64> %src1, <2 x i64> %src2) {
246; CHECK-LABEL: v_or_i64:
247; CHECK:       @ %bb.0: @ %entry
248; CHECK-NEXT:    vorn q0, q1, q0
249; CHECK-NEXT:    bx lr
250entry:
251  %0 = xor <2 x i64> %src1, <i64 -1, i64 -1>
252  %1 = or <2 x i64> %src2, %0
253  ret <2 x i64> %1
254}
255
256