1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
3
4define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
5; CHECK-LABEL: test_vqsubq_u8:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vqsub.u8 q0, q0, q1
8; CHECK-NEXT:    bx lr
9entry:
10  %0 = tail call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %a, <16 x i8> %b)
11  ret <16 x i8> %0
12}
13
14declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1
15
16define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
17; CHECK-LABEL: test_vqsubq_s16:
18; CHECK:       @ %bb.0: @ %entry
19; CHECK-NEXT:    vqsub.s16 q0, q0, q1
20; CHECK-NEXT:    bx lr
21entry:
22  %0 = tail call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a, <8 x i16> %b)
23  ret <8 x i16> %0
24}
25
26declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1
27
28define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
29; CHECK-LABEL: test_vqsubq_u32:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vqsub.u32 q0, q0, q1
32; CHECK-NEXT:    bx lr
33entry:
34  %0 = tail call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
35  ret <4 x i32> %0
36}
37
38declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1
39
40define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
41; CHECK-LABEL: test_vqsubq_m_s8:
42; CHECK:       @ %bb.0: @ %entry
43; CHECK-NEXT:    vmsr p0, r0
44; CHECK-NEXT:    vpst
45; CHECK-NEXT:    vqsubt.s8 q0, q1, q2
46; CHECK-NEXT:    bx lr
47entry:
48  %0 = zext i16 %p to i32
49  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
50  %2 = tail call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive)
51  ret <16 x i8> %2
52}
53
54declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
55
56declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
57
58define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
59; CHECK-LABEL: test_vqsubq_m_u16:
60; CHECK:       @ %bb.0: @ %entry
61; CHECK-NEXT:    vmsr p0, r0
62; CHECK-NEXT:    vpst
63; CHECK-NEXT:    vqsubt.u16 q0, q1, q2
64; CHECK-NEXT:    bx lr
65entry:
66  %0 = zext i16 %p to i32
67  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
68  %2 = tail call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive)
69  ret <8 x i16> %2
70}
71
72declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
73
74declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
75
76define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
77; CHECK-LABEL: test_vqsubq_m_s32:
78; CHECK:       @ %bb.0: @ %entry
79; CHECK-NEXT:    vmsr p0, r0
80; CHECK-NEXT:    vpst
81; CHECK-NEXT:    vqsubt.s32 q0, q1, q2
82; CHECK-NEXT:    bx lr
83entry:
84  %0 = zext i16 %p to i32
85  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
86  %2 = tail call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive)
87  ret <4 x i32> %2
88}
89
90declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
91
92declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
93
94define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> %a, i8 zeroext %b) {
95; CHECK-LABEL: test_vqsubq_n_u8:
96; CHECK:       @ %bb.0: @ %entry
97; CHECK-NEXT:    vqsub.u8 q0, q0, r0
98; CHECK-NEXT:    bx lr
99entry:
100  %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0
101  %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
102  %0 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %a, <16 x i8> %.splat)
103  ret <16 x i8> %0
104}
105
106define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> %a, i16 signext %b) {
107; CHECK-LABEL: test_vqsubq_n_s16:
108; CHECK:       @ %bb.0: @ %entry
109; CHECK-NEXT:    vqsub.s16 q0, q0, r0
110; CHECK-NEXT:    bx lr
111entry:
112  %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0
113  %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
114  %0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a, <8 x i16> %.splat)
115  ret <8 x i16> %0
116}
117
118define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> %a, i32 %b) {
119; CHECK-LABEL: test_vqsubq_n_u32:
120; CHECK:       @ %bb.0: @ %entry
121; CHECK-NEXT:    vqsub.u32 q0, q0, r0
122; CHECK-NEXT:    bx lr
123entry:
124  %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0
125  %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
126  %0 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %.splat)
127  ret <4 x i32> %0
128}
129
130define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i8 signext %b, i16 zeroext %p) {
131; CHECK-LABEL: test_vqsubq_m_n_s8:
132; CHECK:       @ %bb.0: @ %entry
133; CHECK-NEXT:    vmsr p0, r1
134; CHECK-NEXT:    vpst
135; CHECK-NEXT:    vqsubt.s8 q0, q1, r0
136; CHECK-NEXT:    bx lr
137entry:
138  %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0
139  %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
140  %0 = zext i16 %p to i32
141  %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
142  %2 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, i32 0, <16 x i1> %1, <16 x i8> %inactive)
143  ret <16 x i8> %2
144}
145
146define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %b, i16 zeroext %p) {
147; CHECK-LABEL: test_vqsubq_m_n_u16:
148; CHECK:       @ %bb.0: @ %entry
149; CHECK-NEXT:    vmsr p0, r1
150; CHECK-NEXT:    vpst
151; CHECK-NEXT:    vqsubt.u16 q0, q1, r0
152; CHECK-NEXT:    bx lr
153entry:
154  %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0
155  %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
156  %0 = zext i16 %p to i32
157  %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
158  %2 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %.splat, i32 1, <8 x i1> %1, <8 x i16> %inactive)
159  ret <8 x i16> %2
160}
161
162define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i32 %b, i16 zeroext %p) {
163; CHECK-LABEL: test_vqsubq_m_n_s32:
164; CHECK:       @ %bb.0: @ %entry
165; CHECK-NEXT:    vmsr p0, r1
166; CHECK-NEXT:    vpst
167; CHECK-NEXT:    vqsubt.s32 q0, q1, r0
168; CHECK-NEXT:    bx lr
169entry:
170  %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0
171  %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
172  %0 = zext i16 %p to i32
173  %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
174  %2 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, i32 0, <4 x i1> %1, <4 x i32> %inactive)
175  ret <4 x i32> %2
176}
177