1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
3
4; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads.
5
6define arm_aapcs_vfpcc void @k() {
7; CHECK-LABEL: k:
8; CHECK:       @ %bb.0: @ %entry
9; CHECK-NEXT:    .save {r4, r5, r6, lr}
10; CHECK-NEXT:    push {r4, r5, r6, lr}
11; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
12; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
13; CHECK-NEXT:    .pad #16
14; CHECK-NEXT:    sub sp, #16
15; CHECK-NEXT:    adr r5, .LCPI0_0
16; CHECK-NEXT:    adr r4, .LCPI0_1
17; CHECK-NEXT:    vldrw.u32 q5, [r5]
18; CHECK-NEXT:    vldrw.u32 q6, [r4]
19; CHECK-NEXT:    vmov.i32 q0, #0x1
20; CHECK-NEXT:    vmov.i8 q1, #0x0
21; CHECK-NEXT:    vmov.i8 q2, #0xff
22; CHECK-NEXT:    vmov.i16 q3, #0x6
23; CHECK-NEXT:    vmov.i16 q4, #0x3
24; CHECK-NEXT:    movs r0, #0
25; CHECK-NEXT:  .LBB0_1: @ %vector.body
26; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
27; CHECK-NEXT:    vand q5, q5, q0
28; CHECK-NEXT:    vand q6, q6, q0
29; CHECK-NEXT:    vcmp.i32 eq, q5, zr
30; CHECK-NEXT:    vpsel q5, q2, q1
31; CHECK-NEXT:    vcmp.i32 eq, q6, zr
32; CHECK-NEXT:    vpsel q7, q2, q1
33; CHECK-NEXT:    vmov r1, s28
34; CHECK-NEXT:    vmov.16 q6[0], r1
35; CHECK-NEXT:    vmov r1, s29
36; CHECK-NEXT:    vmov.16 q6[1], r1
37; CHECK-NEXT:    vmov r1, s30
38; CHECK-NEXT:    vmov.16 q6[2], r1
39; CHECK-NEXT:    vmov r1, s31
40; CHECK-NEXT:    vmov.16 q6[3], r1
41; CHECK-NEXT:    vmov r1, s20
42; CHECK-NEXT:    vmov.16 q6[4], r1
43; CHECK-NEXT:    vmov r1, s21
44; CHECK-NEXT:    vmov.16 q6[5], r1
45; CHECK-NEXT:    vmov r1, s22
46; CHECK-NEXT:    vmov.16 q6[6], r1
47; CHECK-NEXT:    vmov r1, s23
48; CHECK-NEXT:    vmov.16 q6[7], r1
49; CHECK-NEXT:    vcmp.i16 ne, q6, zr
50; CHECK-NEXT:    vmov.i32 q6, #0x0
51; CHECK-NEXT:    vpsel q5, q4, q3
52; CHECK-NEXT:    vstrh.16 q5, [r0]
53; CHECK-NEXT:    vmov q5, q6
54; CHECK-NEXT:    cbz r0, .LBB0_2
55; CHECK-NEXT:    le .LBB0_1
56; CHECK-NEXT:  .LBB0_2: @ %for.cond4.preheader
57; CHECK-NEXT:    movs r6, #0
58; CHECK-NEXT:    cbnz r6, .LBB0_5
59; CHECK-NEXT:  .LBB0_3: @ %for.body10
60; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
61; CHECK-NEXT:    cbnz r6, .LBB0_4
62; CHECK-NEXT:    le .LBB0_3
63; CHECK-NEXT:  .LBB0_4: @ %for.cond4.loopexit
64; CHECK-NEXT:    bl l
65; CHECK-NEXT:  .LBB0_5: @ %vector.body105.preheader
66; CHECK-NEXT:    vldrw.u32 q0, [r5]
67; CHECK-NEXT:    vldrw.u32 q1, [r4]
68; CHECK-NEXT:    vmov.i32 q2, #0x8
69; CHECK-NEXT:  .LBB0_6: @ %vector.body105
70; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
71; CHECK-NEXT:    vadd.i32 q1, q1, q2
72; CHECK-NEXT:    vadd.i32 q0, q0, q2
73; CHECK-NEXT:    cbz r6, .LBB0_7
74; CHECK-NEXT:    le .LBB0_6
75; CHECK-NEXT:  .LBB0_7: @ %vector.body115.ph
76; CHECK-NEXT:    vldrw.u32 q0, [r4]
77; CHECK-NEXT:    vstrw.32 q0, [sp] @ 16-byte Spill
78; CHECK-NEXT:    @APP
79; CHECK-NEXT:    nop
80; CHECK-NEXT:    @NO_APP
81; CHECK-NEXT:    vldrw.u32 q1, [sp] @ 16-byte Reload
82; CHECK-NEXT:    vmov.i32 q0, #0x4
83; CHECK-NEXT:  .LBB0_8: @ %vector.body115
84; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
85; CHECK-NEXT:    vadd.i32 q1, q1, q0
86; CHECK-NEXT:    b .LBB0_8
87; CHECK-NEXT:    .p2align 4
88; CHECK-NEXT:  @ %bb.9:
89; CHECK-NEXT:  .LCPI0_0:
90; CHECK-NEXT:    .long 4 @ 0x4
91; CHECK-NEXT:    .long 5 @ 0x5
92; CHECK-NEXT:    .long 6 @ 0x6
93; CHECK-NEXT:    .long 7 @ 0x7
94; CHECK-NEXT:  .LCPI0_1:
95; CHECK-NEXT:    .long 0 @ 0x0
96; CHECK-NEXT:    .long 1 @ 0x1
97; CHECK-NEXT:    .long 2 @ 0x2
98; CHECK-NEXT:    .long 3 @ 0x3
99entry:
100  br label %vector.body
101
102vector.body:                                      ; preds = %vector.body, %entry
103  %vec.ind = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %entry ], [ zeroinitializer, %vector.body ]
104  %0 = and <8 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
105  %1 = icmp eq <8 x i32> %0, zeroinitializer
106  %2 = select <8 x i1> %1, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
107  %3 = bitcast i16* undef to <8 x i16>*
108  store <8 x i16> %2, <8 x i16>* %3, align 2
109  %4 = icmp eq i32 undef, 128
110  br i1 %4, label %for.cond4.preheader, label %vector.body
111
112for.cond4.preheader:                              ; preds = %vector.body
113  br i1 undef, label %vector.body105, label %for.body10
114
115for.cond4.loopexit:                               ; preds = %for.body10
116  %call5 = call arm_aapcs_vfpcc i32 bitcast (i32 (...)* @l to i32 ()*)()
117  br label %vector.body105
118
119for.body10:                                       ; preds = %for.body10, %for.cond4.preheader
120  %exitcond88 = icmp eq i32 undef, 7
121  br i1 %exitcond88, label %for.cond4.loopexit, label %for.body10
122
123vector.body105:                                   ; preds = %vector.body105, %for.cond4.loopexit, %for.cond4.preheader
124  %vec.ind113 = phi <8 x i32> [ %vec.ind.next114, %vector.body105 ], [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %for.cond4.loopexit ], [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %for.cond4.preheader ]
125  %5 = and <8 x i32> %vec.ind113, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
126  %vec.ind.next114 = add <8 x i32> %vec.ind113, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
127  %6 = icmp eq i32 undef, 256
128  br i1 %6, label %vector.body115.ph, label %vector.body105
129
130vector.body115.ph:                                ; preds = %vector.body105
131  tail call void asm sideeffect "nop", "~{s0},~{s4},~{s8},~{s12},~{s16},~{s20},~{s24},~{s28},~{memory}"()
132  br label %vector.body115
133
134vector.body115:                                   ; preds = %vector.body115, %vector.body115.ph
135  %vec.ind123 = phi <4 x i32> [ %vec.ind.next124, %vector.body115 ], [ <i32 0, i32 1, i32 2, i32 3>, %vector.body115.ph ]
136  %7 = icmp eq <4 x i32> %vec.ind123, zeroinitializer
137  %vec.ind.next124 = add <4 x i32> %vec.ind123, <i32 4, i32 4, i32 4, i32 4>
138  br label %vector.body115
139}
140
141
142@a = external dso_local global i32, align 4
143@b = dso_local local_unnamed_addr global i32 ptrtoint (i32* @a to i32), align 4
144@c = dso_local global i32 2, align 4
145@d = dso_local global i32 2, align 4
146
147define dso_local i32 @e() #0 {
148; CHECK-LABEL: e:
149; CHECK:       @ %bb.0: @ %entry
150; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}
151; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, lr}
152; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
153; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
154; CHECK-NEXT:    .pad #392
155; CHECK-NEXT:    sub sp, #392
156; CHECK-NEXT:    movw r9, :lower16:.L_MergedGlobals
157; CHECK-NEXT:    vldr s0, .LCPI1_0
158; CHECK-NEXT:    movt r9, :upper16:.L_MergedGlobals
159; CHECK-NEXT:    vldr s3, .LCPI1_1
160; CHECK-NEXT:    mov r5, r9
161; CHECK-NEXT:    mov r7, r9
162; CHECK-NEXT:    ldr r1, [r5, #8]!
163; CHECK-NEXT:    vmov r6, s3
164; CHECK-NEXT:    ldr r0, [r7, #4]!
165; CHECK-NEXT:    movw r4, :lower16:e
166; CHECK-NEXT:    vmov.32 q4[0], r5
167; CHECK-NEXT:    movt r4, :upper16:e
168; CHECK-NEXT:    vmov q1, q4
169; CHECK-NEXT:    vmov s1, r7
170; CHECK-NEXT:    vmov.32 q1[1], r6
171; CHECK-NEXT:    vmov.32 q5[0], r7
172; CHECK-NEXT:    vmov.32 q1[2], r5
173; CHECK-NEXT:    vmov s9, r4
174; CHECK-NEXT:    vmov.32 q1[3], r4
175; CHECK-NEXT:    vdup.32 q6, r7
176; CHECK-NEXT:    vstrw.32 q1, [sp, #76]
177; CHECK-NEXT:    vmov q1, q5
178; CHECK-NEXT:    vmov.32 q1[1], r7
179; CHECK-NEXT:    vmov.f32 s2, s1
180; CHECK-NEXT:    vmov.f32 s8, s0
181; CHECK-NEXT:    vmov.32 q1[2], r6
182; CHECK-NEXT:    vmov q3, q6
183; CHECK-NEXT:    vmov q7, q6
184; CHECK-NEXT:    vmov.f32 s10, s1
185; CHECK-NEXT:    mov.w r8, #4
186; CHECK-NEXT:    mov.w r10, #0
187; CHECK-NEXT:    vmov.32 q1[3], r4
188; CHECK-NEXT:    vmov.32 q3[0], r4
189; CHECK-NEXT:    vmov.32 q7[1], r4
190; CHECK-NEXT:    str r1, [r0]
191; CHECK-NEXT:    vmov.f32 s11, s3
192; CHECK-NEXT:    movs r1, #64
193; CHECK-NEXT:    strh.w r8, [sp, #390]
194; CHECK-NEXT:    strd r0, r10, [sp, #24]
195; CHECK-NEXT:    vstrw.32 q0, [sp, #44]
196; CHECK-NEXT:    str r0, [r0]
197; CHECK-NEXT:    vstrw.32 q2, [r0]
198; CHECK-NEXT:    vstrw.32 q7, [r0]
199; CHECK-NEXT:    vstrw.32 q3, [r0]
200; CHECK-NEXT:    vstrw.32 q1, [r0]
201; CHECK-NEXT:    bl __aeabi_memclr4
202; CHECK-NEXT:    vmov.32 q5[1], r5
203; CHECK-NEXT:    vmov.32 q4[1], r4
204; CHECK-NEXT:    vmov.32 q5[2], r7
205; CHECK-NEXT:    vmov.32 q4[2], r7
206; CHECK-NEXT:    vmov.32 q5[3], r6
207; CHECK-NEXT:    vmov.32 q6[0], r10
208; CHECK-NEXT:    vmov.32 q4[3], r5
209; CHECK-NEXT:    str.w r10, [r9]
210; CHECK-NEXT:    vstrw.32 q4, [r0]
211; CHECK-NEXT:    vstrw.32 q6, [r0]
212; CHECK-NEXT:    vstrw.32 q5, [r0]
213; CHECK-NEXT:    str.w r8, [sp, #308]
214; CHECK-NEXT:  .LBB1_1: @ %for.cond
215; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
216; CHECK-NEXT:    b .LBB1_1
217; CHECK-NEXT:    .p2align 2
218; CHECK-NEXT:  @ %bb.2:
219; CHECK-NEXT:  .LCPI1_0:
220; CHECK-NEXT:    .long 0x00000004 @ float 5.60519386E-45
221; CHECK-NEXT:  .LCPI1_1:
222; CHECK-NEXT:    .long 0x00000000 @ float 0
223entry:
224  %f = alloca i16, align 2
225  %g = alloca [3 x [8 x [4 x i16*]]], align 4
226  store i16 4, i16* %f, align 2
227  %0 = load i32, i32* @c, align 4
228  %1 = load i32, i32* @d, align 4
229  %arrayinit.element7 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 1, i32 1
230  %2 = bitcast i16** %arrayinit.element7 to i32*
231  store i32 %0, i32* %2, align 4
232  %arrayinit.element8 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 1, i32 2
233  store i16* null, i16** %arrayinit.element8, align 4
234  %3 = bitcast i16** undef to i32*
235  store i32 %1, i32* %3, align 4
236  %4 = bitcast i16** undef to i32*
237  store i32 %0, i32* %4, align 4
238  %arrayinit.element13 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 2, i32 2
239  %5 = bitcast i16** %arrayinit.element13 to <4 x i16*>*
240  store <4 x i16*> <i16* inttoptr (i32 4 to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* null>, <4 x i16*>* %5, align 4
241  %arrayinit.element24 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 4, i32 2
242  %6 = bitcast i16** %arrayinit.element24 to <4 x i16*>*
243  store <4 x i16*> <i16* bitcast (i32* @d to i16*), i16* null, i16* bitcast (i32* @d to i16*), i16* bitcast (i32 ()* @e to i16*)>, <4 x i16*>* %6, align 4
244  %7 = bitcast i16** undef to <4 x i16*>*
245  store <4 x i16*> <i16* inttoptr (i32 4 to i16*), i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* null>, <4 x i16*>* %7, align 4
246  %8 = bitcast i16** undef to <4 x i16*>*
247  store <4 x i16*> <i16* bitcast (i32* @c to i16*), i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*)>, <4 x i16*>* %8, align 4
248  %9 = bitcast i16** undef to <4 x i16*>*
249  store <4 x i16*> <i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*)>, <4 x i16*>* %9, align 4
250  %10 = bitcast i16** undef to <4 x i16*>*
251  store <4 x i16*> <i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* null, i16* bitcast (i32 ()* @e to i16*)>, <4 x i16*>* %10, align 4
252  call void @llvm.memset.p0i8.i32(i8* nonnull align 4 dereferenceable(64) undef, i8 0, i32 64, i1 false)
253  %11 = bitcast i16** undef to <4 x i16*>*
254  store <4 x i16*> <i16* bitcast (i32* @d to i16*), i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @d to i16*)>, <4 x i16*>* %11, align 4
255  %12 = bitcast i16** undef to <4 x i16*>*
256  store <4 x i16*> <i16* null, i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*)>, <4 x i16*>* %12, align 4
257  %13 = bitcast i16** undef to <4 x i16*>*
258  store <4 x i16*> <i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @d to i16*), i16* bitcast (i32* @c to i16*), i16* null>, <4 x i16*>* %13, align 4
259  %arrayinit.begin78 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 2, i32 3, i32 0
260  store i16* inttoptr (i32 4 to i16*), i16** %arrayinit.begin78, align 4
261  store i32 0, i32* @b, align 4
262  br label %for.cond
263
264for.cond:                                         ; preds = %for.cond, %entry
265  br label %for.cond
266}
267
268; Function Attrs: argmemonly nounwind willreturn
269declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg) #1
270
271; Function Attrs: argmemonly nounwind willreturn
272declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg) #1
273
274
275declare arm_aapcs_vfpcc i32 @l(...)
276