1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s 3 4--- | 5 define i32* @MVE_VLDRWU32(i32* %x) { unreachable } 6 define i32* @MVE_VLDRHU16(i32* %x) { unreachable } 7 define i32* @MVE_VLDRBU8(i32* %x) { unreachable } 8 define i32* @MVE_VLDRBS32(i32* %x) { unreachable } 9 define i32* @MVE_VLDRBU32(i32* %x) { unreachable } 10 define i32* @MVE_VLDRHS32(i32* %x) { unreachable } 11 define i32* @MVE_VLDRHU32(i32* %x) { unreachable } 12 define i32* @MVE_VLDRBS16(i32* %x) { unreachable } 13 define i32* @MVE_VLDRBU16(i32* %x) { unreachable } 14 define i32* @MVE_VSTRWU32(i32* %x, <4 x i32> %y) { unreachable } 15 define i32* @MVE_VSTRHU16(i32* %x, <4 x i32> %y) { unreachable } 16 define i32* @MVE_VSTRBU8(i32* %x, <4 x i32> %y) { unreachable } 17 define i32* @MVE_VSTRH32(i32* %x, <4 x i32> %y) { unreachable } 18 define i32* @MVE_VSTRB32(i32* %x, <4 x i32> %y) { unreachable } 19 define i32* @MVE_VSTRB16(i32* %x, <4 x i32> %y) { unreachable } 20 21 define i32* @ld0ld4(i32* %x) { unreachable } 22 define i32* @ld4ld0(i32* %x) { unreachable } 23 define i32* @ld0ld4ld0(i32* %x) { unreachable } 24 define i32* @ld4ld0ld4(i32* %x) { unreachable } 25 define i32* @addload(i32* %x) { unreachable } 26 define i32* @sub(i32* %x) { unreachable } 27 define i32* @otherUse(i32* %x) { unreachable } 28 define i32* @postincUse(i32* %x) { unreachable } 29 define i32* @badScale(i32* %x) { unreachable } 30 define i32* @badRange(i32* %x) { unreachable } 31 32 define i32* @addUseOK(i32* %x) { unreachable } 33 define i32* @addUseDom(i32* %x) { unreachable } 34 define i32* @addUseKilled(i32* %x) { unreachable } 35 36 define i32* @MVE_VLDRWU32_post(i32* %x) { unreachable } 37 define i32* @MVE_VLDRHU16_post(i32* %x) { unreachable } 38 define i32* @MVE_VLDRBU8_post(i32* %x) { unreachable } 39 define i32* @MVE_VLDRBS32_post(i32* %x) { unreachable } 40 define i32* @MVE_VLDRBU32_post(i32* %x) { unreachable } 41 define i32* @MVE_VLDRHS32_post(i32* %x) { unreachable } 42 define i32* @MVE_VLDRHU32_post(i32* %x) { unreachable } 43 define i32* @MVE_VLDRBS16_post(i32* %x) { unreachable } 44 define i32* @MVE_VLDRBU16_post(i32* %x) { unreachable } 45 define i32* @MVE_VSTRWU32_post(i32* %x, <4 x i32> %y) { unreachable } 46 define i32* @MVE_VSTRHU16_post(i32* %x, <4 x i32> %y) { unreachable } 47 define i32* @MVE_VSTRBU8_post(i32* %x, <4 x i32> %y) { unreachable } 48 define i32* @MVE_VSTRH32_post(i32* %x, <4 x i32> %y) { unreachable } 49 define i32* @MVE_VSTRB32_post(i32* %x, <4 x i32> %y) { unreachable } 50 define i32* @MVE_VSTRB16_post(i32* %x, <4 x i32> %y) { unreachable } 51 define i32* @MVE_VLDRWU32_pre(i32* %x) { unreachable } 52 define i32* @MVE_VLDRHU16_pre(i32* %x) { unreachable } 53 define i32* @MVE_VLDRBU8_pre(i32* %x) { unreachable } 54 define i32* @MVE_VLDRBS32_pre(i32* %x) { unreachable } 55 define i32* @MVE_VLDRBU32_pre(i32* %x) { unreachable } 56 define i32* @MVE_VLDRHS32_pre(i32* %x) { unreachable } 57 define i32* @MVE_VLDRHU32_pre(i32* %x) { unreachable } 58 define i32* @MVE_VLDRBS16_pre(i32* %x) { unreachable } 59 define i32* @MVE_VLDRBU16_pre(i32* %x) { unreachable } 60 define i32* @MVE_VSTRWU32_pre(i32* %x, <4 x i32> %y) { unreachable } 61 define i32* @MVE_VSTRHU16_pre(i32* %x, <4 x i32> %y) { unreachable } 62 define i32* @MVE_VSTRBU8_pre(i32* %x, <4 x i32> %y) { unreachable } 63 define i32* @MVE_VSTRH32_pre(i32* %x, <4 x i32> %y) { unreachable } 64 define i32* @MVE_VSTRB32_pre(i32* %x, <4 x i32> %y) { unreachable } 65 define i32* @MVE_VSTRB16_pre(i32* %x, <4 x i32> %y) { unreachable } 66 67 define i32* @multiple2(i32* %x) { unreachable } 68 define i32* @multiple3(i32* %x) { unreachable } 69 define i32* @multiple4(i32* %x) { unreachable } 70 define i32* @badScale2(i32* %x) { unreachable } 71 define i32* @badRange2(i32* %x) { unreachable } 72 73... 74--- 75name: MVE_VLDRWU32 76tracksRegLiveness: true 77registers: 78 - { id: 0, class: gprnopc, preferred-register: '' } 79 - { id: 1, class: mqpr, preferred-register: '' } 80 - { id: 2, class: rgpr, preferred-register: '' } 81liveins: 82 - { reg: '$r0', virtual-reg: '%0' } 83 - { reg: '$q0', virtual-reg: '%1' } 84body: | 85 bb.0: 86 liveins: $r0, $q0 87 88 ; CHECK-LABEL: name: MVE_VLDRWU32 89 ; CHECK: liveins: $r0, $q0 90 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 91 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 92 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 93 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 94 %0:gprnopc = COPY $r0 95 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 96 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 97 $r0 = COPY %2 98 tBX_RET 14, $noreg, implicit $r0 99 100... 101--- 102name: MVE_VLDRHU16 103tracksRegLiveness: true 104registers: 105 - { id: 0, class: gprnopc, preferred-register: '' } 106 - { id: 1, class: mqpr, preferred-register: '' } 107 - { id: 2, class: rgpr, preferred-register: '' } 108liveins: 109 - { reg: '$r0', virtual-reg: '%0' } 110 - { reg: '$q0', virtual-reg: '%1' } 111body: | 112 bb.0: 113 liveins: $r0, $q0 114 115 ; CHECK-LABEL: name: MVE_VLDRHU16 116 ; CHECK: liveins: $r0, $q0 117 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 118 ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 119 ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] 120 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 121 %0:gprnopc = COPY $r0 122 %1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg :: (load 16, align 8) 123 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 124 $r0 = COPY %2 125 tBX_RET 14, $noreg, implicit $r0 126 127... 128--- 129name: MVE_VLDRBU8 130tracksRegLiveness: true 131registers: 132 - { id: 0, class: gprnopc, preferred-register: '' } 133 - { id: 1, class: mqpr, preferred-register: '' } 134 - { id: 2, class: rgpr, preferred-register: '' } 135liveins: 136 - { reg: '$r0', virtual-reg: '%0' } 137 - { reg: '$q0', virtual-reg: '%1' } 138body: | 139 bb.0: 140 liveins: $r0, $q0 141 142 ; CHECK-LABEL: name: MVE_VLDRBU8 143 ; CHECK: liveins: $r0, $q0 144 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 145 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 146 ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] 147 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 148 %0:gprnopc = COPY $r0 149 %1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg :: (load 16, align 8) 150 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 151 $r0 = COPY %2 152 tBX_RET 14, $noreg, implicit $r0 153 154... 155--- 156name: MVE_VLDRBS32 157tracksRegLiveness: true 158registers: 159 - { id: 0, class: tgpr, preferred-register: '' } 160 - { id: 1, class: mqpr, preferred-register: '' } 161 - { id: 2, class: rgpr, preferred-register: '' } 162liveins: 163 - { reg: '$r0', virtual-reg: '%0' } 164 - { reg: '$q0', virtual-reg: '%1' } 165body: | 166 bb.0: 167 liveins: $r0, $q0 168 169 ; CHECK-LABEL: name: MVE_VLDRBS32 170 ; CHECK: liveins: $r0, $q0 171 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 172 ; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg :: (load 4, align 8) 173 ; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]] 174 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 175 %0:tgpr = COPY $r0 176 %1:mqpr = MVE_VLDRBS32 %0, 0, 0, $noreg :: (load 4, align 8) 177 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 178 $r0 = COPY %2 179 tBX_RET 14, $noreg, implicit $r0 180 181... 182--- 183name: MVE_VLDRBU32 184tracksRegLiveness: true 185registers: 186 - { id: 0, class: tgpr, preferred-register: '' } 187 - { id: 1, class: mqpr, preferred-register: '' } 188 - { id: 2, class: rgpr, preferred-register: '' } 189liveins: 190 - { reg: '$r0', virtual-reg: '%0' } 191 - { reg: '$q0', virtual-reg: '%1' } 192body: | 193 bb.0: 194 liveins: $r0, $q0 195 196 ; CHECK-LABEL: name: MVE_VLDRBU32 197 ; CHECK: liveins: $r0, $q0 198 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 199 ; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg :: (load 4, align 8) 200 ; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]] 201 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 202 %0:tgpr = COPY $r0 203 %1:mqpr = MVE_VLDRBU32 %0, 0, 0, $noreg :: (load 4, align 8) 204 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 205 $r0 = COPY %2 206 tBX_RET 14, $noreg, implicit $r0 207 208... 209--- 210name: MVE_VLDRHS32 211tracksRegLiveness: true 212registers: 213 - { id: 0, class: tgpr, preferred-register: '' } 214 - { id: 1, class: mqpr, preferred-register: '' } 215 - { id: 2, class: rgpr, preferred-register: '' } 216liveins: 217 - { reg: '$r0', virtual-reg: '%0' } 218 - { reg: '$q0', virtual-reg: '%1' } 219body: | 220 bb.0: 221 liveins: $r0, $q0 222 223 ; CHECK-LABEL: name: MVE_VLDRHS32 224 ; CHECK: liveins: $r0, $q0 225 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 226 ; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg :: (load 8) 227 ; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]] 228 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 229 %0:tgpr = COPY $r0 230 %1:mqpr = MVE_VLDRHS32 %0, 0, 0, $noreg :: (load 8, align 8) 231 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 232 $r0 = COPY %2 233 tBX_RET 14, $noreg, implicit $r0 234 235... 236--- 237name: MVE_VLDRHU32 238tracksRegLiveness: true 239registers: 240 - { id: 0, class: tgpr, preferred-register: '' } 241 - { id: 1, class: mqpr, preferred-register: '' } 242 - { id: 2, class: rgpr, preferred-register: '' } 243liveins: 244 - { reg: '$r0', virtual-reg: '%0' } 245 - { reg: '$q0', virtual-reg: '%1' } 246body: | 247 bb.0: 248 liveins: $r0, $q0 249 250 ; CHECK-LABEL: name: MVE_VLDRHU32 251 ; CHECK: liveins: $r0, $q0 252 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 253 ; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg :: (load 8) 254 ; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]] 255 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 256 %0:tgpr = COPY $r0 257 %1:mqpr = MVE_VLDRHU32 %0, 0, 0, $noreg :: (load 8, align 8) 258 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 259 $r0 = COPY %2 260 tBX_RET 14, $noreg, implicit $r0 261 262... 263--- 264name: MVE_VLDRBS16 265tracksRegLiveness: true 266registers: 267 - { id: 0, class: tgpr, preferred-register: '' } 268 - { id: 1, class: mqpr, preferred-register: '' } 269 - { id: 2, class: rgpr, preferred-register: '' } 270liveins: 271 - { reg: '$r0', virtual-reg: '%0' } 272 - { reg: '$q0', virtual-reg: '%1' } 273body: | 274 bb.0: 275 liveins: $r0, $q0 276 277 ; CHECK-LABEL: name: MVE_VLDRBS16 278 ; CHECK: liveins: $r0, $q0 279 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 280 ; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg :: (load 8) 281 ; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]] 282 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 283 %0:tgpr = COPY $r0 284 %1:mqpr = MVE_VLDRBS16 %0, 0, 0, $noreg :: (load 8, align 8) 285 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 286 $r0 = COPY %2 287 tBX_RET 14, $noreg, implicit $r0 288 289... 290--- 291name: MVE_VLDRBU16 292tracksRegLiveness: true 293registers: 294 - { id: 0, class: tgpr, preferred-register: '' } 295 - { id: 1, class: mqpr, preferred-register: '' } 296 - { id: 2, class: rgpr, preferred-register: '' } 297liveins: 298 - { reg: '$r0', virtual-reg: '%0' } 299 - { reg: '$q0', virtual-reg: '%1' } 300body: | 301 bb.0: 302 liveins: $r0, $q0 303 304 ; CHECK-LABEL: name: MVE_VLDRBU16 305 ; CHECK: liveins: $r0, $q0 306 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 307 ; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg :: (load 8) 308 ; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]] 309 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 310 %0:tgpr = COPY $r0 311 %1:mqpr = MVE_VLDRBU16 %0, 0, 0, $noreg :: (load 8, align 8) 312 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 313 $r0 = COPY %2 314 tBX_RET 14, $noreg, implicit $r0 315 316... 317--- 318name: MVE_VSTRWU32 319tracksRegLiveness: true 320registers: 321 - { id: 0, class: gprnopc, preferred-register: '' } 322 - { id: 1, class: mqpr, preferred-register: '' } 323 - { id: 2, class: rgpr, preferred-register: '' } 324liveins: 325 - { reg: '$r0', virtual-reg: '%0' } 326 - { reg: '$q0', virtual-reg: '%1' } 327body: | 328 bb.0: 329 liveins: $r0, $q0 330 331 ; CHECK-LABEL: name: MVE_VSTRWU32 332 ; CHECK: liveins: $r0, $q0 333 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 334 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 335 ; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 336 ; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]] 337 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 338 %1:mqpr = COPY $q0 339 %0:gprnopc = COPY $r0 340 MVE_VSTRWU32 %1, %0, 0, 0, $noreg :: (store 16, align 8) 341 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 342 $r0 = COPY %2 343 tBX_RET 14, $noreg, implicit $r0 344 345... 346--- 347name: MVE_VSTRHU16 348tracksRegLiveness: true 349registers: 350 - { id: 0, class: gprnopc, preferred-register: '' } 351 - { id: 1, class: mqpr, preferred-register: '' } 352 - { id: 2, class: rgpr, preferred-register: '' } 353liveins: 354 - { reg: '$r0', virtual-reg: '%0' } 355 - { reg: '$q0', virtual-reg: '%1' } 356body: | 357 bb.0: 358 liveins: $r0, $q0 359 360 ; CHECK-LABEL: name: MVE_VSTRHU16 361 ; CHECK: liveins: $r0, $q0 362 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 363 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 364 ; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 365 ; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]] 366 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 367 %1:mqpr = COPY $q0 368 %0:gprnopc = COPY $r0 369 MVE_VSTRHU16 %1, %0, 0, 0, $noreg :: (store 16, align 8) 370 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 371 $r0 = COPY %2 372 tBX_RET 14, $noreg, implicit $r0 373 374... 375--- 376name: MVE_VSTRBU8 377tracksRegLiveness: true 378registers: 379 - { id: 0, class: gprnopc, preferred-register: '' } 380 - { id: 1, class: mqpr, preferred-register: '' } 381 - { id: 2, class: rgpr, preferred-register: '' } 382liveins: 383 - { reg: '$r0', virtual-reg: '%0' } 384 - { reg: '$q0', virtual-reg: '%1' } 385body: | 386 bb.0: 387 liveins: $r0, $q0 388 389 ; CHECK-LABEL: name: MVE_VSTRBU8 390 ; CHECK: liveins: $r0, $q0 391 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 392 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 393 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 394 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]] 395 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 396 %1:mqpr = COPY $q0 397 %0:gprnopc = COPY $r0 398 MVE_VSTRBU8 %1, %0, 0, 0, $noreg :: (store 16, align 8) 399 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 400 $r0 = COPY %2 401 tBX_RET 14, $noreg, implicit $r0 402 403... 404--- 405name: MVE_VSTRH32 406tracksRegLiveness: true 407registers: 408 - { id: 0, class: tgpr, preferred-register: '' } 409 - { id: 1, class: mqpr, preferred-register: '' } 410 - { id: 2, class: rgpr, preferred-register: '' } 411liveins: 412 - { reg: '$r0', virtual-reg: '%0' } 413 - { reg: '$q0', virtual-reg: '%1' } 414body: | 415 bb.0: 416 liveins: $r0, $q0 417 418 ; CHECK-LABEL: name: MVE_VSTRH32 419 ; CHECK: liveins: $r0, $q0 420 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 421 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 422 ; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 8) 423 ; CHECK: $r0 = COPY [[MVE_VSTRH32_post]] 424 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 425 %1:mqpr = COPY $q0 426 %0:tgpr = COPY $r0 427 MVE_VSTRH32 %1, %0, 0, 0, $noreg :: (store 8, align 8) 428 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 429 $r0 = COPY %2 430 tBX_RET 14, $noreg, implicit $r0 431 432... 433--- 434name: MVE_VSTRB32 435tracksRegLiveness: true 436registers: 437 - { id: 0, class: tgpr, preferred-register: '' } 438 - { id: 1, class: mqpr, preferred-register: '' } 439 - { id: 2, class: rgpr, preferred-register: '' } 440liveins: 441 - { reg: '$r0', virtual-reg: '%0' } 442 - { reg: '$q0', virtual-reg: '%1' } 443body: | 444 bb.0: 445 liveins: $r0, $q0 446 447 ; CHECK-LABEL: name: MVE_VSTRB32 448 ; CHECK: liveins: $r0, $q0 449 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 450 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 451 ; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 4, align 8) 452 ; CHECK: $r0 = COPY [[MVE_VSTRB32_post]] 453 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 454 %1:mqpr = COPY $q0 455 %0:tgpr = COPY $r0 456 MVE_VSTRB32 %1, %0, 0, 0, $noreg :: (store 4, align 8) 457 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 458 $r0 = COPY %2 459 tBX_RET 14, $noreg, implicit $r0 460 461... 462--- 463name: MVE_VSTRB16 464tracksRegLiveness: true 465registers: 466 - { id: 0, class: tgpr, preferred-register: '' } 467 - { id: 1, class: mqpr, preferred-register: '' } 468 - { id: 2, class: rgpr, preferred-register: '' } 469liveins: 470 - { reg: '$r0', virtual-reg: '%0' } 471 - { reg: '$q0', virtual-reg: '%1' } 472body: | 473 bb.0: 474 liveins: $r0, $q0 475 476 ; CHECK-LABEL: name: MVE_VSTRB16 477 ; CHECK: liveins: $r0, $q0 478 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 479 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 480 ; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 8) 481 ; CHECK: $r0 = COPY [[MVE_VSTRB16_post]] 482 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 483 %1:mqpr = COPY $q0 484 %0:tgpr = COPY $r0 485 MVE_VSTRB16 %1, %0, 0, 0, $noreg :: (store 8, align 8) 486 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 487 $r0 = COPY %2 488 tBX_RET 14, $noreg, implicit $r0 489 490... 491--- 492name: ld0ld4 493tracksRegLiveness: true 494registers: 495 - { id: 0, class: gprnopc, preferred-register: '' } 496 - { id: 1, class: mqpr, preferred-register: '' } 497 - { id: 2, class: rgpr, preferred-register: '' } 498 - { id: 3, class: mqpr, preferred-register: '' } 499liveins: 500 - { reg: '$r0', virtual-reg: '%0' } 501 - { reg: '$q0', virtual-reg: '%1' } 502body: | 503 bb.0: 504 liveins: $r0, $q0 505 506 ; CHECK-LABEL: name: ld0ld4 507 ; CHECK: liveins: $r0, $q0 508 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 509 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 510 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) 511 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 512 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 513 %0:gprnopc = COPY $r0 514 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 515 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 516 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 517 $r0 = COPY %2 518 tBX_RET 14, $noreg, implicit $r0 519 520... 521--- 522name: ld4ld0 523tracksRegLiveness: true 524registers: 525 - { id: 0, class: gprnopc, preferred-register: '' } 526 - { id: 1, class: mqpr, preferred-register: '' } 527 - { id: 2, class: rgpr, preferred-register: '' } 528 - { id: 3, class: mqpr, preferred-register: '' } 529liveins: 530 - { reg: '$r0', virtual-reg: '%0' } 531 - { reg: '$q0', virtual-reg: '%1' } 532body: | 533 bb.0: 534 liveins: $r0, $q0 535 536 ; CHECK-LABEL: name: ld4ld0 537 ; CHECK: liveins: $r0, $q0 538 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 539 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) 540 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 541 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 542 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 543 %0:gprnopc = COPY $r0 544 %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 545 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 546 %3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 547 $r0 = COPY %2 548 tBX_RET 14, $noreg, implicit $r0 549 550... 551--- 552name: ld0ld4ld0 553tracksRegLiveness: true 554registers: 555 - { id: 0, class: gprnopc, preferred-register: '' } 556 - { id: 1, class: mqpr, preferred-register: '' } 557 - { id: 2, class: rgpr, preferred-register: '' } 558 - { id: 3, class: mqpr, preferred-register: '' } 559 - { id: 4, class: mqpr, preferred-register: '' } 560liveins: 561 - { reg: '$r0', virtual-reg: '%0' } 562 - { reg: '$q0', virtual-reg: '%1' } 563body: | 564 bb.0: 565 liveins: $r0, $q0 566 567 ; CHECK-LABEL: name: ld0ld4ld0 568 ; CHECK: liveins: $r0, $q0 569 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 570 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) 571 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) 572 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 573 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 574 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 575 %0:gprnopc = COPY $r0 576 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 577 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 578 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 579 %4:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 580 $r0 = COPY %2 581 tBX_RET 14, $noreg, implicit $r0 582 583... 584--- 585name: ld4ld0ld4 586tracksRegLiveness: true 587registers: 588 - { id: 0, class: gprnopc, preferred-register: '' } 589 - { id: 1, class: mqpr, preferred-register: '' } 590 - { id: 2, class: rgpr, preferred-register: '' } 591 - { id: 3, class: mqpr, preferred-register: '' } 592 - { id: 4, class: mqpr, preferred-register: '' } 593liveins: 594 - { reg: '$r0', virtual-reg: '%0' } 595 - { reg: '$q0', virtual-reg: '%1' } 596body: | 597 bb.0: 598 liveins: $r0, $q0 599 600 ; CHECK-LABEL: name: ld4ld0ld4 601 ; CHECK: liveins: $r0, $q0 602 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 603 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) 604 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 605 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) 606 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 607 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 608 %0:gprnopc = COPY $r0 609 %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 610 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 611 %3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 612 %4:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 613 $r0 = COPY %2 614 tBX_RET 14, $noreg, implicit $r0 615 616... 617--- 618name: addload 619tracksRegLiveness: true 620registers: 621 - { id: 0, class: gprnopc, preferred-register: '' } 622 - { id: 1, class: mqpr, preferred-register: '' } 623 - { id: 2, class: rgpr, preferred-register: '' } 624 - { id: 3, class: mqpr, preferred-register: '' } 625liveins: 626 - { reg: '$r0', virtual-reg: '%0' } 627 - { reg: '$q0', virtual-reg: '%1' } 628body: | 629 bb.0: 630 liveins: $r0, $q0 631 632 ; CHECK-LABEL: name: addload 633 ; CHECK: liveins: $r0, $q0 634 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 635 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 636 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) 637 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 638 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 639 %0:gprnopc = COPY $r0 640 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 641 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 642 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 643 $r0 = COPY %2 644 tBX_RET 14, $noreg, implicit $r0 645 646... 647--- 648name: sub 649tracksRegLiveness: true 650registers: 651 - { id: 0, class: gprnopc, preferred-register: '' } 652 - { id: 1, class: mqpr, preferred-register: '' } 653 - { id: 2, class: rgpr, preferred-register: '' } 654 - { id: 3, class: mqpr, preferred-register: '' } 655liveins: 656 - { reg: '$r0', virtual-reg: '%0' } 657 - { reg: '$q0', virtual-reg: '%1' } 658body: | 659 bb.0: 660 liveins: $r0, $q0 661 662 ; CHECK-LABEL: name: sub 663 ; CHECK: liveins: $r0, $q0 664 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 665 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) 666 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) 667 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 668 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 669 %0:gprnopc = COPY $r0 670 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 671 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 672 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 673 $r0 = COPY %2 674 tBX_RET 14, $noreg, implicit $r0 675 676... 677--- 678name: otherUse 679tracksRegLiveness: true 680registers: 681 - { id: 0, class: gprnopc, preferred-register: '' } 682 - { id: 1, class: mqpr, preferred-register: '' } 683 - { id: 2, class: rgpr, preferred-register: '' } 684 - { id: 3, class: mqpr, preferred-register: '' } 685liveins: 686 - { reg: '$r0', virtual-reg: '%0' } 687 - { reg: '$q0', virtual-reg: '%1' } 688body: | 689 bb.0: 690 liveins: $r0, $q0 691 692 ; CHECK-LABEL: name: otherUse 693 ; CHECK: liveins: $r0, $q0 694 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 695 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 696 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) 697 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) 698 ; CHECK: $r0 = COPY [[COPY]] 699 ; CHECK: $r0 = COPY [[t2ADDri]] 700 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 701 %0:gprnopc = COPY $r0 702 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 703 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 704 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 705 $r0 = COPY %0 706 $r0 = COPY %2 707 tBX_RET 14, $noreg, implicit $r0 708 709... 710--- 711name: postincUse 712tracksRegLiveness: true 713registers: 714 - { id: 0, class: gprnopc, preferred-register: '' } 715 - { id: 1, class: mqpr, preferred-register: '' } 716 - { id: 2, class: rgpr, preferred-register: '' } 717 - { id: 3, class: mqpr, preferred-register: '' } 718 - { id: 4, class: rgpr, preferred-register: '' } 719liveins: 720 - { reg: '$r0', virtual-reg: '%0' } 721 - { reg: '$q0', virtual-reg: '%1' } 722body: | 723 bb.0: 724 liveins: $r0, $q0 725 726 ; CHECK-LABEL: name: postincUse 727 ; CHECK: liveins: $r0, $q0 728 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 729 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 730 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) 731 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg :: (load 16, align 8) 732 ; CHECK: $r0 = COPY [[t2ADDri]] 733 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 734 %0:gprnopc = COPY $r0 735 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 736 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 737 %4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg :: (load 16, align 8) 738 $r0 = COPY %2 739 tBX_RET 14, $noreg, implicit $r0 740 741... 742--- 743name: badScale 744tracksRegLiveness: true 745registers: 746 - { id: 0, class: gprnopc, preferred-register: '' } 747 - { id: 1, class: mqpr, preferred-register: '' } 748 - { id: 2, class: rgpr, preferred-register: '' } 749 - { id: 3, class: mqpr, preferred-register: '' } 750liveins: 751 - { reg: '$r0', virtual-reg: '%0' } 752 - { reg: '$q0', virtual-reg: '%1' } 753body: | 754 bb.0: 755 liveins: $r0, $q0 756 757 ; CHECK-LABEL: name: badScale 758 ; CHECK: liveins: $r0, $q0 759 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 760 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) 761 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 3, 14 /* CC::al */, $noreg, $noreg 762 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) 763 ; CHECK: $r0 = COPY [[t2SUBri]] 764 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 765 %0:gprnopc = COPY $r0 766 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 767 %2:rgpr = nuw t2SUBri %0, 3, 14, $noreg, $noreg 768 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 769 $r0 = COPY %2 770 tBX_RET 14, $noreg, implicit $r0 771 772... 773--- 774name: badRange 775tracksRegLiveness: true 776registers: 777 - { id: 0, class: gprnopc, preferred-register: '' } 778 - { id: 1, class: mqpr, preferred-register: '' } 779 - { id: 2, class: rgpr, preferred-register: '' } 780 - { id: 3, class: mqpr, preferred-register: '' } 781liveins: 782 - { reg: '$r0', virtual-reg: '%0' } 783 - { reg: '$q0', virtual-reg: '%1' } 784body: | 785 bb.0: 786 liveins: $r0, $q0 787 788 ; CHECK-LABEL: name: badRange 789 ; CHECK: liveins: $r0, $q0 790 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 791 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) 792 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], -300, 14 /* CC::al */, $noreg, $noreg 793 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], -300, 0, $noreg :: (load 16, align 8) 794 ; CHECK: $r0 = COPY [[t2SUBri]] 795 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 796 %0:gprnopc = COPY $r0 797 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 798 %2:rgpr = nuw t2SUBri %0, -300, 14, $noreg, $noreg 799 %3:mqpr = MVE_VLDRWU32 %0, -300, 0, $noreg :: (load 16, align 8) 800 $r0 = COPY %2 801 tBX_RET 14, $noreg, implicit $r0 802 803... 804--- 805name: addUseOK 806tracksRegLiveness: true 807registers: 808 - { id: 0, class: gprnopc, preferred-register: '' } 809 - { id: 1, class: mqpr, preferred-register: '' } 810 - { id: 2, class: rgpr, preferred-register: '' } 811 - { id: 3, class: mqpr, preferred-register: '' } 812 - { id: 4, class: rgpr, preferred-register: '' } 813liveins: 814 - { reg: '$r0', virtual-reg: '%0' } 815 - { reg: '$q0', virtual-reg: '%1' } 816body: | 817 bb.0: 818 liveins: $r0, $q0 819 820 ; CHECK-LABEL: name: addUseOK 821 ; CHECK: liveins: $r0, $q0 822 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 823 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) 824 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) 825 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg 826 ; CHECK: $r0 = COPY [[t2LSRri]] 827 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 828 %0:gprnopc = COPY $r0 829 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 830 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 831 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 832 %4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg 833 $r0 = COPY %4 834 tBX_RET 14, $noreg, implicit $r0 835 836... 837--- 838name: addUseDom 839tracksRegLiveness: true 840registers: 841 - { id: 0, class: gprnopc, preferred-register: '' } 842 - { id: 1, class: mqpr, preferred-register: '' } 843 - { id: 2, class: rgpr, preferred-register: '' } 844 - { id: 3, class: mqpr, preferred-register: '' } 845 - { id: 4, class: rgpr, preferred-register: '' } 846liveins: 847 - { reg: '$r0', virtual-reg: '%0' } 848 - { reg: '$q0', virtual-reg: '%1' } 849body: | 850 bb.0: 851 liveins: $r0, $q0 852 853 ; CHECK-LABEL: name: addUseDom 854 ; CHECK: liveins: $r0, $q0 855 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 856 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 857 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg 858 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) 859 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) 860 ; CHECK: $r0 = COPY [[t2LSRri]] 861 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 862 %0:gprnopc = COPY $r0 863 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 864 %4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg 865 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 866 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 867 $r0 = COPY %4 868 tBX_RET 14, $noreg, implicit $r0 869 870... 871--- 872name: addUseKilled 873tracksRegLiveness: true 874registers: 875 - { id: 0, class: gprnopc, preferred-register: '' } 876 - { id: 1, class: mqpr, preferred-register: '' } 877 - { id: 2, class: rgpr, preferred-register: '' } 878 - { id: 3, class: mqpr, preferred-register: '' } 879 - { id: 4, class: rgpr, preferred-register: '' } 880liveins: 881 - { reg: '$r0', virtual-reg: '%0' } 882 - { reg: '$q0', virtual-reg: '%1' } 883body: | 884 bb.0: 885 liveins: $r0, $q0 886 887 ; CHECK-LABEL: name: addUseKilled 888 ; CHECK: liveins: $r0, $q0 889 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 890 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) 891 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg 892 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) 893 ; CHECK: $r0 = COPY [[t2LSRri]] 894 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 895 %0:gprnopc = COPY $r0 896 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) 897 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 898 %4:rgpr = nuw t2LSRri killed %2, 2, 14, $noreg, $noreg 899 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) 900 $r0 = COPY %4 901 tBX_RET 14, $noreg, implicit $r0 902 903... 904--- 905name: MVE_VLDRWU32_post 906tracksRegLiveness: true 907registers: 908 - { id: 0, class: gprnopc, preferred-register: '' } 909 - { id: 1, class: mqpr, preferred-register: '' } 910 - { id: 2, class: rgpr, preferred-register: '' } 911liveins: 912 - { reg: '$r0', virtual-reg: '%0' } 913 - { reg: '$q0', virtual-reg: '%1' } 914body: | 915 bb.0: 916 liveins: $r0, $q0 917 918 ; CHECK-LABEL: name: MVE_VLDRWU32_post 919 ; CHECK: liveins: $r0, $q0 920 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 921 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 922 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg :: (load 16, align 8) 923 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] 924 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 925 %0:gprnopc = COPY $r0 926 %2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg :: (load 16, align 8) 927 %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load 16, align 8) 928 $r0 = COPY %2 929 tBX_RET 14, $noreg, implicit $r0 930 931... 932--- 933name: MVE_VLDRHU16_post 934tracksRegLiveness: true 935registers: 936 - { id: 0, class: gprnopc, preferred-register: '' } 937 - { id: 1, class: mqpr, preferred-register: '' } 938 - { id: 2, class: rgpr, preferred-register: '' } 939liveins: 940 - { reg: '$r0', virtual-reg: '%0' } 941 - { reg: '$q0', virtual-reg: '%1' } 942body: | 943 bb.0: 944 liveins: $r0, $q0 945 946 ; CHECK-LABEL: name: MVE_VLDRHU16_post 947 ; CHECK: liveins: $r0, $q0 948 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 949 ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 950 ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg :: (load 16, align 8) 951 ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] 952 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 953 %0:gprnopc = COPY $r0 954 %2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg :: (load 16, align 8) 955 %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load 16, align 8) 956 $r0 = COPY %2 957 tBX_RET 14, $noreg, implicit $r0 958 959... 960--- 961name: MVE_VLDRBU8_post 962tracksRegLiveness: true 963registers: 964 - { id: 0, class: gprnopc, preferred-register: '' } 965 - { id: 1, class: mqpr, preferred-register: '' } 966 - { id: 2, class: rgpr, preferred-register: '' } 967liveins: 968 - { reg: '$r0', virtual-reg: '%0' } 969 - { reg: '$q0', virtual-reg: '%1' } 970body: | 971 bb.0: 972 liveins: $r0, $q0 973 974 ; CHECK-LABEL: name: MVE_VLDRBU8_post 975 ; CHECK: liveins: $r0, $q0 976 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 977 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 978 ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg :: (load 16, align 8) 979 ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] 980 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 981 %0:gprnopc = COPY $r0 982 %2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg :: (load 16, align 8) 983 %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load 16, align 8) 984 $r0 = COPY %2 985 tBX_RET 14, $noreg, implicit $r0 986 987... 988--- 989name: MVE_VLDRBS32_post 990tracksRegLiveness: true 991registers: 992 - { id: 0, class: tgpr, preferred-register: '' } 993 - { id: 1, class: mqpr, preferred-register: '' } 994 - { id: 2, class: tgpr, preferred-register: '' } 995liveins: 996 - { reg: '$r0', virtual-reg: '%0' } 997 - { reg: '$q0', virtual-reg: '%1' } 998body: | 999 bb.0: 1000 liveins: $r0, $q0 1001 1002 ; CHECK-LABEL: name: MVE_VLDRBS32_post 1003 ; CHECK: liveins: $r0, $q0 1004 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1005 ; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1006 ; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_post]], -16, 0, $noreg :: (load 16, align 8) 1007 ; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]] 1008 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1009 %0:tgpr = COPY $r0 1010 %2:tgpr, %1:mqpr = MVE_VLDRBS32_post %0, 32, 0, $noreg :: (load 16, align 8) 1011 %1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg :: (load 16, align 8) 1012 $r0 = COPY %2 1013 tBX_RET 14, $noreg, implicit $r0 1014 1015... 1016--- 1017name: MVE_VLDRBU32_post 1018tracksRegLiveness: true 1019registers: 1020 - { id: 0, class: tgpr, preferred-register: '' } 1021 - { id: 1, class: mqpr, preferred-register: '' } 1022 - { id: 2, class: tgpr, preferred-register: '' } 1023liveins: 1024 - { reg: '$r0', virtual-reg: '%0' } 1025 - { reg: '$q0', virtual-reg: '%1' } 1026body: | 1027 bb.0: 1028 liveins: $r0, $q0 1029 1030 ; CHECK-LABEL: name: MVE_VLDRBU32_post 1031 ; CHECK: liveins: $r0, $q0 1032 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1033 ; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1034 ; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_post]], -16, 0, $noreg :: (load 16, align 8) 1035 ; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]] 1036 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1037 %0:tgpr = COPY $r0 1038 %2:tgpr, %1:mqpr = MVE_VLDRBU32_post %0, 32, 0, $noreg :: (load 16, align 8) 1039 %1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg :: (load 16, align 8) 1040 $r0 = COPY %2 1041 tBX_RET 14, $noreg, implicit $r0 1042 1043... 1044--- 1045name: MVE_VLDRHS32_post 1046tracksRegLiveness: true 1047registers: 1048 - { id: 0, class: tgpr, preferred-register: '' } 1049 - { id: 1, class: mqpr, preferred-register: '' } 1050 - { id: 2, class: tgpr, preferred-register: '' } 1051liveins: 1052 - { reg: '$r0', virtual-reg: '%0' } 1053 - { reg: '$q0', virtual-reg: '%1' } 1054body: | 1055 bb.0: 1056 liveins: $r0, $q0 1057 1058 ; CHECK-LABEL: name: MVE_VLDRHS32_post 1059 ; CHECK: liveins: $r0, $q0 1060 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1061 ; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1062 ; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_post]], -16, 0, $noreg :: (load 16, align 8) 1063 ; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]] 1064 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1065 %0:tgpr = COPY $r0 1066 %2:tgpr, %1:mqpr = MVE_VLDRHS32_post %0, 32, 0, $noreg :: (load 16, align 8) 1067 %1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg :: (load 16, align 8) 1068 $r0 = COPY %2 1069 tBX_RET 14, $noreg, implicit $r0 1070 1071... 1072--- 1073name: MVE_VLDRHU32_post 1074tracksRegLiveness: true 1075registers: 1076 - { id: 0, class: tgpr, preferred-register: '' } 1077 - { id: 1, class: mqpr, preferred-register: '' } 1078 - { id: 2, class: tgpr, preferred-register: '' } 1079liveins: 1080 - { reg: '$r0', virtual-reg: '%0' } 1081 - { reg: '$q0', virtual-reg: '%1' } 1082body: | 1083 bb.0: 1084 liveins: $r0, $q0 1085 1086 ; CHECK-LABEL: name: MVE_VLDRHU32_post 1087 ; CHECK: liveins: $r0, $q0 1088 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1089 ; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1090 ; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_post]], -16, 0, $noreg :: (load 16, align 8) 1091 ; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]] 1092 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1093 %0:tgpr = COPY $r0 1094 %2:tgpr, %1:mqpr = MVE_VLDRHU32_post %0, 32, 0, $noreg :: (load 16, align 8) 1095 %1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg :: (load 16, align 8) 1096 $r0 = COPY %2 1097 tBX_RET 14, $noreg, implicit $r0 1098 1099... 1100--- 1101name: MVE_VLDRBS16_post 1102tracksRegLiveness: true 1103registers: 1104 - { id: 0, class: tgpr, preferred-register: '' } 1105 - { id: 1, class: mqpr, preferred-register: '' } 1106 - { id: 2, class: tgpr, preferred-register: '' } 1107liveins: 1108 - { reg: '$r0', virtual-reg: '%0' } 1109 - { reg: '$q0', virtual-reg: '%1' } 1110body: | 1111 bb.0: 1112 liveins: $r0, $q0 1113 1114 ; CHECK-LABEL: name: MVE_VLDRBS16_post 1115 ; CHECK: liveins: $r0, $q0 1116 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1117 ; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1118 ; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_post]], -16, 0, $noreg :: (load 16, align 8) 1119 ; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]] 1120 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1121 %0:tgpr = COPY $r0 1122 %2:tgpr, %1:mqpr = MVE_VLDRBS16_post %0, 32, 0, $noreg :: (load 16, align 8) 1123 %1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg :: (load 16, align 8) 1124 $r0 = COPY %2 1125 tBX_RET 14, $noreg, implicit $r0 1126 1127... 1128--- 1129name: MVE_VLDRBU16_post 1130tracksRegLiveness: true 1131registers: 1132 - { id: 0, class: tgpr, preferred-register: '' } 1133 - { id: 1, class: mqpr, preferred-register: '' } 1134 - { id: 2, class: tgpr, preferred-register: '' } 1135liveins: 1136 - { reg: '$r0', virtual-reg: '%0' } 1137 - { reg: '$q0', virtual-reg: '%1' } 1138body: | 1139 bb.0: 1140 liveins: $r0, $q0 1141 1142 ; CHECK-LABEL: name: MVE_VLDRBU16_post 1143 ; CHECK: liveins: $r0, $q0 1144 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1145 ; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1146 ; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_post]], -16, 0, $noreg :: (load 16, align 8) 1147 ; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]] 1148 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1149 %0:tgpr = COPY $r0 1150 %2:tgpr, %1:mqpr = MVE_VLDRBU16_post %0, 32, 0, $noreg :: (load 16, align 8) 1151 %1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg :: (load 16, align 8) 1152 $r0 = COPY %2 1153 tBX_RET 14, $noreg, implicit $r0 1154 1155... 1156--- 1157name: MVE_VSTRWU32_post 1158tracksRegLiveness: true 1159registers: 1160 - { id: 0, class: rgpr, preferred-register: '' } 1161 - { id: 1, class: mqpr, preferred-register: '' } 1162 - { id: 2, class: rgpr, preferred-register: '' } 1163liveins: 1164 - { reg: '$r0', virtual-reg: '%0' } 1165 - { reg: '$q0', virtual-reg: '%1' } 1166body: | 1167 bb.0: 1168 liveins: $r0, $q0 1169 1170 ; CHECK-LABEL: name: MVE_VSTRWU32_post 1171 ; CHECK: liveins: $r0, $q0 1172 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1173 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 1174 ; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1175 ; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_post]], -16, 0, $noreg :: (store 16, align 8) 1176 ; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]] 1177 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1178 %1:mqpr = COPY $q0 1179 %0:rgpr = COPY $r0 1180 %2:rgpr = MVE_VSTRWU32_post %1, %0, 32, 0, $noreg :: (store 16, align 8) 1181 MVE_VSTRWU32 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1182 $r0 = COPY %2 1183 tBX_RET 14, $noreg, implicit $r0 1184 1185... 1186--- 1187name: MVE_VSTRHU16_post 1188tracksRegLiveness: true 1189registers: 1190 - { id: 0, class: rgpr, preferred-register: '' } 1191 - { id: 1, class: mqpr, preferred-register: '' } 1192 - { id: 2, class: rgpr, preferred-register: '' } 1193liveins: 1194 - { reg: '$r0', virtual-reg: '%0' } 1195 - { reg: '$q0', virtual-reg: '%1' } 1196body: | 1197 bb.0: 1198 liveins: $r0, $q0 1199 1200 ; CHECK-LABEL: name: MVE_VSTRHU16_post 1201 ; CHECK: liveins: $r0, $q0 1202 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1203 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 1204 ; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1205 ; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_post]], -16, 0, $noreg :: (store 16, align 8) 1206 ; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]] 1207 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1208 %1:mqpr = COPY $q0 1209 %0:rgpr = COPY $r0 1210 %2:rgpr = MVE_VSTRHU16_post %1, %0, 32, 0, $noreg :: (store 16, align 8) 1211 MVE_VSTRHU16 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1212 $r0 = COPY %2 1213 tBX_RET 14, $noreg, implicit $r0 1214 1215... 1216--- 1217name: MVE_VSTRBU8_post 1218tracksRegLiveness: true 1219registers: 1220 - { id: 0, class: rgpr, preferred-register: '' } 1221 - { id: 1, class: mqpr, preferred-register: '' } 1222 - { id: 2, class: rgpr, preferred-register: '' } 1223liveins: 1224 - { reg: '$r0', virtual-reg: '%0' } 1225 - { reg: '$q0', virtual-reg: '%1' } 1226body: | 1227 bb.0: 1228 liveins: $r0, $q0 1229 1230 ; CHECK-LABEL: name: MVE_VSTRBU8_post 1231 ; CHECK: liveins: $r0, $q0 1232 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1233 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 1234 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1235 ; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_post]], -16, 0, $noreg :: (store 16, align 8) 1236 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]] 1237 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1238 %1:mqpr = COPY $q0 1239 %0:rgpr = COPY $r0 1240 %2:rgpr = MVE_VSTRBU8_post %1, %0, 32, 0, $noreg :: (store 16, align 8) 1241 MVE_VSTRBU8 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1242 $r0 = COPY %2 1243 tBX_RET 14, $noreg, implicit $r0 1244 1245... 1246--- 1247name: MVE_VSTRH32_post 1248tracksRegLiveness: true 1249registers: 1250 - { id: 0, class: tgpr, preferred-register: '' } 1251 - { id: 1, class: mqpr, preferred-register: '' } 1252 - { id: 2, class: tgpr, preferred-register: '' } 1253liveins: 1254 - { reg: '$r0', virtual-reg: '%0' } 1255 - { reg: '$q0', virtual-reg: '%1' } 1256body: | 1257 bb.0: 1258 liveins: $r0, $q0 1259 1260 ; CHECK-LABEL: name: MVE_VSTRH32_post 1261 ; CHECK: liveins: $r0, $q0 1262 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1263 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1264 ; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1265 ; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_post]], -16, 0, $noreg :: (store 16, align 8) 1266 ; CHECK: $r0 = COPY [[MVE_VSTRH32_post]] 1267 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1268 %1:mqpr = COPY $q0 1269 %0:tgpr = COPY $r0 1270 %2:tgpr = MVE_VSTRH32_post %1, %0, 32, 0, $noreg :: (store 16, align 8) 1271 MVE_VSTRH32 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1272 $r0 = COPY %2 1273 tBX_RET 14, $noreg, implicit $r0 1274 1275... 1276--- 1277name: MVE_VSTRB32_post 1278tracksRegLiveness: true 1279registers: 1280 - { id: 0, class: tgpr, preferred-register: '' } 1281 - { id: 1, class: mqpr, preferred-register: '' } 1282 - { id: 2, class: tgpr, preferred-register: '' } 1283liveins: 1284 - { reg: '$r0', virtual-reg: '%0' } 1285 - { reg: '$q0', virtual-reg: '%1' } 1286body: | 1287 bb.0: 1288 liveins: $r0, $q0 1289 1290 ; CHECK-LABEL: name: MVE_VSTRB32_post 1291 ; CHECK: liveins: $r0, $q0 1292 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1293 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1294 ; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1295 ; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_post]], -16, 0, $noreg :: (store 16, align 8) 1296 ; CHECK: $r0 = COPY [[MVE_VSTRB32_post]] 1297 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1298 %1:mqpr = COPY $q0 1299 %0:tgpr = COPY $r0 1300 %2:tgpr = MVE_VSTRB32_post %1, %0, 32, 0, $noreg :: (store 16, align 8) 1301 MVE_VSTRB32 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1302 $r0 = COPY %2 1303 tBX_RET 14, $noreg, implicit $r0 1304 1305... 1306--- 1307name: MVE_VSTRB16_post 1308tracksRegLiveness: true 1309registers: 1310 - { id: 0, class: tgpr, preferred-register: '' } 1311 - { id: 1, class: mqpr, preferred-register: '' } 1312 - { id: 2, class: tgpr, preferred-register: '' } 1313liveins: 1314 - { reg: '$r0', virtual-reg: '%0' } 1315 - { reg: '$q0', virtual-reg: '%1' } 1316body: | 1317 bb.0: 1318 liveins: $r0, $q0 1319 1320 ; CHECK-LABEL: name: MVE_VSTRB16_post 1321 ; CHECK: liveins: $r0, $q0 1322 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1323 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1324 ; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1325 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_post]], -16, 0, $noreg :: (store 16, align 8) 1326 ; CHECK: $r0 = COPY [[MVE_VSTRB16_post]] 1327 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1328 %1:mqpr = COPY $q0 1329 %0:tgpr = COPY $r0 1330 %2:tgpr = MVE_VSTRB16_post %1, %0, 32, 0, $noreg :: (store 16, align 8) 1331 MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1332 $r0 = COPY %2 1333 tBX_RET 14, $noreg, implicit $r0 1334 1335... 1336--- 1337name: MVE_VLDRWU32_pre 1338tracksRegLiveness: true 1339registers: 1340 - { id: 0, class: rgpr, preferred-register: '' } 1341 - { id: 1, class: mqpr, preferred-register: '' } 1342 - { id: 2, class: rgpr, preferred-register: '' } 1343liveins: 1344 - { reg: '$r0', virtual-reg: '%0' } 1345 - { reg: '$q0', virtual-reg: '%1' } 1346body: | 1347 bb.0: 1348 liveins: $r0, $q0 1349 1350 ; CHECK-LABEL: name: MVE_VLDRWU32_pre 1351 ; CHECK: liveins: $r0, $q0 1352 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 1353 ; CHECK: [[MVE_VLDRWU32_pre:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRWU32_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1354 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_pre]], -16, 0, $noreg :: (load 16, align 8) 1355 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_pre]] 1356 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1357 %0:rgpr = COPY $r0 1358 %2:rgpr, %1:mqpr = MVE_VLDRWU32_pre %0, 32, 0, $noreg :: (load 16, align 8) 1359 %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load 16, align 8) 1360 $r0 = COPY %2 1361 tBX_RET 14, $noreg, implicit $r0 1362 1363... 1364--- 1365name: MVE_VLDRHU16_pre 1366tracksRegLiveness: true 1367registers: 1368 - { id: 0, class: rgpr, preferred-register: '' } 1369 - { id: 1, class: mqpr, preferred-register: '' } 1370 - { id: 2, class: rgpr, preferred-register: '' } 1371liveins: 1372 - { reg: '$r0', virtual-reg: '%0' } 1373 - { reg: '$q0', virtual-reg: '%1' } 1374body: | 1375 bb.0: 1376 liveins: $r0, $q0 1377 1378 ; CHECK-LABEL: name: MVE_VLDRHU16_pre 1379 ; CHECK: liveins: $r0, $q0 1380 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 1381 ; CHECK: [[MVE_VLDRHU16_pre:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU16_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1382 ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_pre]], -16, 0, $noreg :: (load 16, align 8) 1383 ; CHECK: $r0 = COPY [[MVE_VLDRHU16_pre]] 1384 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1385 %0:rgpr = COPY $r0 1386 %2:rgpr, %1:mqpr = MVE_VLDRHU16_pre %0, 32, 0, $noreg :: (load 16, align 8) 1387 %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load 16, align 8) 1388 $r0 = COPY %2 1389 tBX_RET 14, $noreg, implicit $r0 1390 1391... 1392--- 1393name: MVE_VLDRBU8_pre 1394tracksRegLiveness: true 1395registers: 1396 - { id: 0, class: rgpr, preferred-register: '' } 1397 - { id: 1, class: mqpr, preferred-register: '' } 1398 - { id: 2, class: rgpr, preferred-register: '' } 1399liveins: 1400 - { reg: '$r0', virtual-reg: '%0' } 1401 - { reg: '$q0', virtual-reg: '%1' } 1402body: | 1403 bb.0: 1404 liveins: $r0, $q0 1405 1406 ; CHECK-LABEL: name: MVE_VLDRBU8_pre 1407 ; CHECK: liveins: $r0, $q0 1408 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 1409 ; CHECK: [[MVE_VLDRBU8_pre:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU8_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1410 ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_pre]], -16, 0, $noreg :: (load 16, align 8) 1411 ; CHECK: $r0 = COPY [[MVE_VLDRBU8_pre]] 1412 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1413 %0:rgpr = COPY $r0 1414 %2:rgpr, %1:mqpr = MVE_VLDRBU8_pre %0, 32, 0, $noreg :: (load 16, align 8) 1415 %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load 16, align 8) 1416 $r0 = COPY %2 1417 tBX_RET 14, $noreg, implicit $r0 1418 1419... 1420--- 1421name: MVE_VLDRBS32_pre 1422tracksRegLiveness: true 1423registers: 1424 - { id: 0, class: tgpr, preferred-register: '' } 1425 - { id: 1, class: mqpr, preferred-register: '' } 1426 - { id: 2, class: tgpr, preferred-register: '' } 1427liveins: 1428 - { reg: '$r0', virtual-reg: '%0' } 1429 - { reg: '$q0', virtual-reg: '%1' } 1430body: | 1431 bb.0: 1432 liveins: $r0, $q0 1433 1434 ; CHECK-LABEL: name: MVE_VLDRBS32_pre 1435 ; CHECK: liveins: $r0, $q0 1436 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1437 ; CHECK: [[MVE_VLDRBS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS32_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1438 ; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_pre]], -16, 0, $noreg :: (load 16, align 8) 1439 ; CHECK: $r0 = COPY [[MVE_VLDRBS32_pre]] 1440 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1441 %0:tgpr = COPY $r0 1442 %2:tgpr, %1:mqpr = MVE_VLDRBS32_pre %0, 32, 0, $noreg :: (load 16, align 8) 1443 %1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg :: (load 16, align 8) 1444 $r0 = COPY %2 1445 tBX_RET 14, $noreg, implicit $r0 1446 1447... 1448--- 1449name: MVE_VLDRBU32_pre 1450tracksRegLiveness: true 1451registers: 1452 - { id: 0, class: tgpr, preferred-register: '' } 1453 - { id: 1, class: mqpr, preferred-register: '' } 1454 - { id: 2, class: tgpr, preferred-register: '' } 1455liveins: 1456 - { reg: '$r0', virtual-reg: '%0' } 1457 - { reg: '$q0', virtual-reg: '%1' } 1458body: | 1459 bb.0: 1460 liveins: $r0, $q0 1461 1462 ; CHECK-LABEL: name: MVE_VLDRBU32_pre 1463 ; CHECK: liveins: $r0, $q0 1464 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1465 ; CHECK: [[MVE_VLDRBU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU32_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1466 ; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_pre]], -16, 0, $noreg :: (load 16, align 8) 1467 ; CHECK: $r0 = COPY [[MVE_VLDRBU32_pre]] 1468 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1469 %0:tgpr = COPY $r0 1470 %2:tgpr, %1:mqpr = MVE_VLDRBU32_pre %0, 32, 0, $noreg :: (load 16, align 8) 1471 %1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg :: (load 16, align 8) 1472 $r0 = COPY %2 1473 tBX_RET 14, $noreg, implicit $r0 1474 1475... 1476--- 1477name: MVE_VLDRHS32_pre 1478tracksRegLiveness: true 1479registers: 1480 - { id: 0, class: tgpr, preferred-register: '' } 1481 - { id: 1, class: mqpr, preferred-register: '' } 1482 - { id: 2, class: tgpr, preferred-register: '' } 1483liveins: 1484 - { reg: '$r0', virtual-reg: '%0' } 1485 - { reg: '$q0', virtual-reg: '%1' } 1486body: | 1487 bb.0: 1488 liveins: $r0, $q0 1489 1490 ; CHECK-LABEL: name: MVE_VLDRHS32_pre 1491 ; CHECK: liveins: $r0, $q0 1492 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1493 ; CHECK: [[MVE_VLDRHS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHS32_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1494 ; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_pre]], -16, 0, $noreg :: (load 16, align 8) 1495 ; CHECK: $r0 = COPY [[MVE_VLDRHS32_pre]] 1496 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1497 %0:tgpr = COPY $r0 1498 %2:tgpr, %1:mqpr = MVE_VLDRHS32_pre %0, 32, 0, $noreg :: (load 16, align 8) 1499 %1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg :: (load 16, align 8) 1500 $r0 = COPY %2 1501 tBX_RET 14, $noreg, implicit $r0 1502 1503... 1504--- 1505name: MVE_VLDRHU32_pre 1506tracksRegLiveness: true 1507registers: 1508 - { id: 0, class: tgpr, preferred-register: '' } 1509 - { id: 1, class: mqpr, preferred-register: '' } 1510 - { id: 2, class: tgpr, preferred-register: '' } 1511liveins: 1512 - { reg: '$r0', virtual-reg: '%0' } 1513 - { reg: '$q0', virtual-reg: '%1' } 1514body: | 1515 bb.0: 1516 liveins: $r0, $q0 1517 1518 ; CHECK-LABEL: name: MVE_VLDRHU32_pre 1519 ; CHECK: liveins: $r0, $q0 1520 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1521 ; CHECK: [[MVE_VLDRHU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU32_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1522 ; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_pre]], -16, 0, $noreg :: (load 16, align 8) 1523 ; CHECK: $r0 = COPY [[MVE_VLDRHU32_pre]] 1524 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1525 %0:tgpr = COPY $r0 1526 %2:tgpr, %1:mqpr = MVE_VLDRHU32_pre %0, 32, 0, $noreg :: (load 16, align 8) 1527 %1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg :: (load 16, align 8) 1528 $r0 = COPY %2 1529 tBX_RET 14, $noreg, implicit $r0 1530 1531... 1532--- 1533name: MVE_VLDRBS16_pre 1534tracksRegLiveness: true 1535registers: 1536 - { id: 0, class: tgpr, preferred-register: '' } 1537 - { id: 1, class: mqpr, preferred-register: '' } 1538 - { id: 2, class: tgpr, preferred-register: '' } 1539liveins: 1540 - { reg: '$r0', virtual-reg: '%0' } 1541 - { reg: '$q0', virtual-reg: '%1' } 1542body: | 1543 bb.0: 1544 liveins: $r0, $q0 1545 1546 ; CHECK-LABEL: name: MVE_VLDRBS16_pre 1547 ; CHECK: liveins: $r0, $q0 1548 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1549 ; CHECK: [[MVE_VLDRBS16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS16_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1550 ; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_pre]], -16, 0, $noreg :: (load 16, align 8) 1551 ; CHECK: $r0 = COPY [[MVE_VLDRBS16_pre]] 1552 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1553 %0:tgpr = COPY $r0 1554 %2:tgpr, %1:mqpr = MVE_VLDRBS16_pre %0, 32, 0, $noreg :: (load 16, align 8) 1555 %1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg :: (load 16, align 8) 1556 $r0 = COPY %2 1557 tBX_RET 14, $noreg, implicit $r0 1558 1559... 1560--- 1561name: MVE_VLDRBU16_pre 1562tracksRegLiveness: true 1563registers: 1564 - { id: 0, class: tgpr, preferred-register: '' } 1565 - { id: 1, class: mqpr, preferred-register: '' } 1566 - { id: 2, class: tgpr, preferred-register: '' } 1567liveins: 1568 - { reg: '$r0', virtual-reg: '%0' } 1569 - { reg: '$q0', virtual-reg: '%1' } 1570body: | 1571 bb.0: 1572 liveins: $r0, $q0 1573 1574 ; CHECK-LABEL: name: MVE_VLDRBU16_pre 1575 ; CHECK: liveins: $r0, $q0 1576 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 1577 ; CHECK: [[MVE_VLDRBU16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU16_pre [[COPY]], 32, 0, $noreg :: (load 16, align 8) 1578 ; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_pre]], -16, 0, $noreg :: (load 16, align 8) 1579 ; CHECK: $r0 = COPY [[MVE_VLDRBU16_pre]] 1580 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1581 %0:tgpr = COPY $r0 1582 %2:tgpr, %1:mqpr = MVE_VLDRBU16_pre %0, 32, 0, $noreg :: (load 16, align 8) 1583 %1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg :: (load 16, align 8) 1584 $r0 = COPY %2 1585 tBX_RET 14, $noreg, implicit $r0 1586 1587... 1588--- 1589name: MVE_VSTRWU32_pre 1590tracksRegLiveness: true 1591registers: 1592 - { id: 0, class: rgpr, preferred-register: '' } 1593 - { id: 1, class: mqpr, preferred-register: '' } 1594 - { id: 2, class: rgpr, preferred-register: '' } 1595liveins: 1596 - { reg: '$r0', virtual-reg: '%0' } 1597 - { reg: '$q0', virtual-reg: '%1' } 1598body: | 1599 bb.0: 1600 liveins: $r0, $q0 1601 1602 ; CHECK-LABEL: name: MVE_VSTRWU32_pre 1603 ; CHECK: liveins: $r0, $q0 1604 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1605 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 1606 ; CHECK: [[MVE_VSTRWU32_pre:%[0-9]+]]:rgpr = MVE_VSTRWU32_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1607 ; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_pre]], -16, 0, $noreg :: (store 16, align 8) 1608 ; CHECK: $r0 = COPY [[MVE_VSTRWU32_pre]] 1609 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1610 %1:mqpr = COPY $q0 1611 %0:rgpr = COPY $r0 1612 %2:rgpr = MVE_VSTRWU32_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1613 MVE_VSTRWU32 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1614 $r0 = COPY %2 1615 tBX_RET 14, $noreg, implicit $r0 1616 1617... 1618--- 1619name: MVE_VSTRHU16_pre 1620tracksRegLiveness: true 1621registers: 1622 - { id: 0, class: rgpr, preferred-register: '' } 1623 - { id: 1, class: mqpr, preferred-register: '' } 1624 - { id: 2, class: rgpr, preferred-register: '' } 1625liveins: 1626 - { reg: '$r0', virtual-reg: '%0' } 1627 - { reg: '$q0', virtual-reg: '%1' } 1628body: | 1629 bb.0: 1630 liveins: $r0, $q0 1631 1632 ; CHECK-LABEL: name: MVE_VSTRHU16_pre 1633 ; CHECK: liveins: $r0, $q0 1634 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1635 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 1636 ; CHECK: [[MVE_VSTRHU16_pre:%[0-9]+]]:rgpr = MVE_VSTRHU16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1637 ; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_pre]], -16, 0, $noreg :: (store 16, align 8) 1638 ; CHECK: $r0 = COPY [[MVE_VSTRHU16_pre]] 1639 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1640 %1:mqpr = COPY $q0 1641 %0:rgpr = COPY $r0 1642 %2:rgpr = MVE_VSTRHU16_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1643 MVE_VSTRHU16 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1644 $r0 = COPY %2 1645 tBX_RET 14, $noreg, implicit $r0 1646 1647... 1648--- 1649name: MVE_VSTRBU8_pre 1650tracksRegLiveness: true 1651registers: 1652 - { id: 0, class: rgpr, preferred-register: '' } 1653 - { id: 1, class: mqpr, preferred-register: '' } 1654 - { id: 2, class: rgpr, preferred-register: '' } 1655liveins: 1656 - { reg: '$r0', virtual-reg: '%0' } 1657 - { reg: '$q0', virtual-reg: '%1' } 1658body: | 1659 bb.0: 1660 liveins: $r0, $q0 1661 1662 ; CHECK-LABEL: name: MVE_VSTRBU8_pre 1663 ; CHECK: liveins: $r0, $q0 1664 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1665 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 1666 ; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:rgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1667 ; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_pre]], -16, 0, $noreg :: (store 16, align 8) 1668 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]] 1669 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1670 %1:mqpr = COPY $q0 1671 %0:rgpr = COPY $r0 1672 %2:rgpr = MVE_VSTRBU8_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1673 MVE_VSTRBU8 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1674 $r0 = COPY %2 1675 tBX_RET 14, $noreg, implicit $r0 1676 1677... 1678--- 1679name: MVE_VSTRH32_pre 1680tracksRegLiveness: true 1681registers: 1682 - { id: 0, class: tgpr, preferred-register: '' } 1683 - { id: 1, class: mqpr, preferred-register: '' } 1684 - { id: 2, class: tgpr, preferred-register: '' } 1685liveins: 1686 - { reg: '$r0', virtual-reg: '%0' } 1687 - { reg: '$q0', virtual-reg: '%1' } 1688body: | 1689 bb.0: 1690 liveins: $r0, $q0 1691 1692 ; CHECK-LABEL: name: MVE_VSTRH32_pre 1693 ; CHECK: liveins: $r0, $q0 1694 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1695 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1696 ; CHECK: [[MVE_VSTRH32_pre:%[0-9]+]]:tgpr = MVE_VSTRH32_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1697 ; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_pre]], -16, 0, $noreg :: (store 16, align 8) 1698 ; CHECK: $r0 = COPY [[MVE_VSTRH32_pre]] 1699 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1700 %1:mqpr = COPY $q0 1701 %0:tgpr = COPY $r0 1702 %2:tgpr = MVE_VSTRH32_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1703 MVE_VSTRH32 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1704 $r0 = COPY %2 1705 tBX_RET 14, $noreg, implicit $r0 1706 1707... 1708--- 1709name: MVE_VSTRB32_pre 1710tracksRegLiveness: true 1711registers: 1712 - { id: 0, class: tgpr, preferred-register: '' } 1713 - { id: 1, class: mqpr, preferred-register: '' } 1714 - { id: 2, class: tgpr, preferred-register: '' } 1715liveins: 1716 - { reg: '$r0', virtual-reg: '%0' } 1717 - { reg: '$q0', virtual-reg: '%1' } 1718body: | 1719 bb.0: 1720 liveins: $r0, $q0 1721 1722 ; CHECK-LABEL: name: MVE_VSTRB32_pre 1723 ; CHECK: liveins: $r0, $q0 1724 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1725 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1726 ; CHECK: [[MVE_VSTRB32_pre:%[0-9]+]]:tgpr = MVE_VSTRB32_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1727 ; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_pre]], -16, 0, $noreg :: (store 16, align 8) 1728 ; CHECK: $r0 = COPY [[MVE_VSTRB32_pre]] 1729 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1730 %1:mqpr = COPY $q0 1731 %0:tgpr = COPY $r0 1732 %2:tgpr = MVE_VSTRB32_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1733 MVE_VSTRB32 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1734 $r0 = COPY %2 1735 tBX_RET 14, $noreg, implicit $r0 1736 1737... 1738--- 1739name: MVE_VSTRB16_pre 1740tracksRegLiveness: true 1741registers: 1742 - { id: 0, class: tgpr, preferred-register: '' } 1743 - { id: 1, class: mqpr, preferred-register: '' } 1744 - { id: 2, class: tgpr, preferred-register: '' } 1745liveins: 1746 - { reg: '$r0', virtual-reg: '%0' } 1747 - { reg: '$q0', virtual-reg: '%1' } 1748body: | 1749 bb.0: 1750 liveins: $r0, $q0 1751 1752 ; CHECK-LABEL: name: MVE_VSTRB16_pre 1753 ; CHECK: liveins: $r0, $q0 1754 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1755 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1756 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1757 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg :: (store 16, align 8) 1758 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]] 1759 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1760 %1:mqpr = COPY $q0 1761 %0:tgpr = COPY $r0 1762 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1763 MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1764 $r0 = COPY %2 1765 tBX_RET 14, $noreg, implicit $r0 1766 1767... 1768--- 1769name: multiple2 1770tracksRegLiveness: true 1771registers: 1772 - { id: 0, class: tgpr, preferred-register: '' } 1773 - { id: 1, class: mqpr, preferred-register: '' } 1774 - { id: 2, class: tgpr, preferred-register: '' } 1775liveins: 1776 - { reg: '$r0', virtual-reg: '%0' } 1777 - { reg: '$q0', virtual-reg: '%1' } 1778body: | 1779 bb.0: 1780 liveins: $r0, $q0 1781 1782 ; CHECK-LABEL: name: multiple2 1783 ; CHECK: liveins: $r0, $q0 1784 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1785 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1786 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1787 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg :: (store 16, align 8) 1788 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -48, 0, $noreg :: (store 16, align 8) 1789 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], 2, 0, $noreg :: (store 16, align 8) 1790 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]] 1791 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1792 %1:mqpr = COPY $q0 1793 %0:tgpr = COPY $r0 1794 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1795 MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1796 MVE_VSTRB16 %1, %0, -16, 0, $noreg :: (store 16, align 8) 1797 MVE_VSTRB16 %1, %0, 34, 0, $noreg :: (store 16, align 8) 1798 $r0 = COPY %2 1799 tBX_RET 14, $noreg, implicit $r0 1800 1801... 1802--- 1803name: multiple3 1804tracksRegLiveness: true 1805registers: 1806 - { id: 0, class: tgpr, preferred-register: '' } 1807 - { id: 1, class: mqpr, preferred-register: '' } 1808 - { id: 2, class: tgpr, preferred-register: '' } 1809 - { id: 3, class: tgpr, preferred-register: '' } 1810liveins: 1811 - { reg: '$r0', virtual-reg: '%0' } 1812 - { reg: '$q0', virtual-reg: '%1' } 1813body: | 1814 bb.0: 1815 liveins: $r0, $q0 1816 1817 ; CHECK-LABEL: name: multiple3 1818 ; CHECK: liveins: $r0, $q0 1819 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1820 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1821 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1822 ; CHECK: [[MVE_VSTRB16_pre1:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 64, 0, $noreg :: (store 16, align 8) 1823 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre1]], -48, 0, $noreg :: (store 16, align 8) 1824 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre1]] 1825 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1826 %1:mqpr = COPY $q0 1827 %0:tgpr = COPY $r0 1828 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1829 %3:tgpr = MVE_VSTRB16_pre %1, %0, 64, 0, $noreg :: (store 16, align 8) 1830 MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store 16, align 8) 1831 $r0 = COPY %3 1832 tBX_RET 14, $noreg, implicit $r0 1833 1834... 1835--- 1836name: multiple4 1837tracksRegLiveness: true 1838registers: 1839 - { id: 0, class: tgpr, preferred-register: '' } 1840 - { id: 1, class: mqpr, preferred-register: '' } 1841 - { id: 2, class: tgpr, preferred-register: '' } 1842 - { id: 3, class: tgpr, preferred-register: '' } 1843liveins: 1844 - { reg: '$r0', virtual-reg: '%0' } 1845 - { reg: '$q0', virtual-reg: '%1' } 1846body: | 1847 bb.0: 1848 liveins: $r0, $q0 1849 1850 ; CHECK-LABEL: name: multiple4 1851 ; CHECK: liveins: $r0, $q0 1852 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1853 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1854 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) 1855 ; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8) 1856 ; CHECK: [[t2ADDri:%[0-9]+]]:tgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg 1857 ; CHECK: $r0 = COPY [[t2ADDri]] 1858 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1859 %1:mqpr = COPY $q0 1860 %0:tgpr = COPY $r0 1861 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store 16, align 8) 1862 MVE_VSTRB16 %1, %0, 0, 0, $noreg :: (store 16, align 8) 1863 %3:tgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 1864 $r0 = COPY %3 1865 tBX_RET 14, $noreg, implicit $r0 1866 1867... 1868--- 1869name: badScale2 1870tracksRegLiveness: true 1871registers: 1872 - { id: 0, class: tgpr, preferred-register: '' } 1873 - { id: 1, class: mqpr, preferred-register: '' } 1874 - { id: 2, class: tgpr, preferred-register: '' } 1875liveins: 1876 - { reg: '$r0', virtual-reg: '%0' } 1877 - { reg: '$q0', virtual-reg: '%1' } 1878body: | 1879 bb.0: 1880 liveins: $r0, $q0 1881 1882 ; CHECK-LABEL: name: badScale2 1883 ; CHECK: liveins: $r0, $q0 1884 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1885 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1886 ; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:tgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 33, 0, $noreg :: (store 16, align 8) 1887 ; CHECK: MVE_VSTRWU32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8) 1888 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]] 1889 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1890 %1:mqpr = COPY $q0 1891 %0:tgpr = COPY $r0 1892 %2:tgpr = MVE_VSTRBU8_pre %1, %0, 33, 0, $noreg :: (store 16, align 8) 1893 MVE_VSTRWU32 %1, %0, 0, 0, $noreg :: (store 16, align 8) 1894 $r0 = COPY %2 1895 tBX_RET 14, $noreg, implicit $r0 1896 1897... 1898--- 1899name: badRange2 1900tracksRegLiveness: true 1901registers: 1902 - { id: 0, class: tgpr, preferred-register: '' } 1903 - { id: 1, class: mqpr, preferred-register: '' } 1904 - { id: 2, class: tgpr, preferred-register: '' } 1905liveins: 1906 - { reg: '$r0', virtual-reg: '%0' } 1907 - { reg: '$q0', virtual-reg: '%1' } 1908body: | 1909 bb.0: 1910 liveins: $r0, $q0 1911 1912 ; CHECK-LABEL: name: badRange2 1913 ; CHECK: liveins: $r0, $q0 1914 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 1915 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 1916 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 100, 0, $noreg :: (store 16, align 8) 1917 ; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], -100, 0, $noreg :: (store 16, align 8) 1918 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]] 1919 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 1920 %1:mqpr = COPY $q0 1921 %0:tgpr = COPY $r0 1922 %2:tgpr = MVE_VSTRB16_pre %1, %0, 100, 0, $noreg :: (store 16, align 8) 1923 MVE_VSTRB16 %1, %0, -100, 0, $noreg :: (store 16, align 8) 1924 $r0 = COPY %2 1925 tBX_RET 14, $noreg, implicit $r0 1926 1927... 1928