1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { 5; CHECK-LABEL: cmpeqz_v4i1: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vpt.i32 ne, q0, zr 8; CHECK-NEXT: vcmpt.i32 ne, q1, zr 9; CHECK-NEXT: vpsel q0, q1, q0 10; CHECK-NEXT: bx lr 11entry: 12 %c1 = icmp eq <4 x i32> %a, zeroinitializer 13 %c2 = icmp eq <4 x i32> %b, zeroinitializer 14 %o = or <4 x i1> %c1, %c2 15 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 16 ret <4 x i32> %s 17} 18 19define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) { 20; CHECK-LABEL: cmpnez_v4i1: 21; CHECK: @ %bb.0: @ %entry 22; CHECK-NEXT: vpt.i32 ne, q0, zr 23; CHECK-NEXT: vcmpt.i32 eq, q1, zr 24; CHECK-NEXT: vpsel q0, q1, q0 25; CHECK-NEXT: bx lr 26entry: 27 %c1 = icmp eq <4 x i32> %a, zeroinitializer 28 %c2 = icmp ne <4 x i32> %b, zeroinitializer 29 %o = or <4 x i1> %c1, %c2 30 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 31 ret <4 x i32> %s 32} 33 34define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) { 35; CHECK-LABEL: cmpsltz_v4i1: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: vpt.i32 ne, q0, zr 38; CHECK-NEXT: vcmpt.s32 ge, q1, zr 39; CHECK-NEXT: vpsel q0, q1, q0 40; CHECK-NEXT: bx lr 41entry: 42 %c1 = icmp eq <4 x i32> %a, zeroinitializer 43 %c2 = icmp slt <4 x i32> %b, zeroinitializer 44 %o = or <4 x i1> %c1, %c2 45 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 46 ret <4 x i32> %s 47} 48 49define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) { 50; CHECK-LABEL: cmpsgtz_v4i1: 51; CHECK: @ %bb.0: @ %entry 52; CHECK-NEXT: vpt.i32 ne, q0, zr 53; CHECK-NEXT: vcmpt.s32 le, q1, zr 54; CHECK-NEXT: vpsel q0, q1, q0 55; CHECK-NEXT: bx lr 56entry: 57 %c1 = icmp eq <4 x i32> %a, zeroinitializer 58 %c2 = icmp sgt <4 x i32> %b, zeroinitializer 59 %o = or <4 x i1> %c1, %c2 60 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 61 ret <4 x i32> %s 62} 63 64define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) { 65; CHECK-LABEL: cmpslez_v4i1: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: vpt.i32 ne, q0, zr 68; CHECK-NEXT: vcmpt.s32 gt, q1, zr 69; CHECK-NEXT: vpsel q0, q1, q0 70; CHECK-NEXT: bx lr 71entry: 72 %c1 = icmp eq <4 x i32> %a, zeroinitializer 73 %c2 = icmp sle <4 x i32> %b, zeroinitializer 74 %o = or <4 x i1> %c1, %c2 75 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 76 ret <4 x i32> %s 77} 78 79define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) { 80; CHECK-LABEL: cmpsgez_v4i1: 81; CHECK: @ %bb.0: @ %entry 82; CHECK-NEXT: vpt.i32 ne, q0, zr 83; CHECK-NEXT: vcmpt.s32 lt, q1, zr 84; CHECK-NEXT: vpsel q0, q1, q0 85; CHECK-NEXT: bx lr 86entry: 87 %c1 = icmp eq <4 x i32> %a, zeroinitializer 88 %c2 = icmp sge <4 x i32> %b, zeroinitializer 89 %o = or <4 x i1> %c1, %c2 90 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 91 ret <4 x i32> %s 92} 93 94define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) { 95; CHECK-LABEL: cmpultz_v4i1: 96; CHECK: @ %bb.0: @ %entry 97; CHECK-NEXT: vcmp.i32 eq, q0, zr 98; CHECK-NEXT: vpsel q0, q0, q1 99; CHECK-NEXT: bx lr 100entry: 101 %c1 = icmp eq <4 x i32> %a, zeroinitializer 102 %c2 = icmp ult <4 x i32> %b, zeroinitializer 103 %o = or <4 x i1> %c1, %c2 104 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 105 ret <4 x i32> %s 106} 107 108define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) { 109; CHECK-LABEL: cmpugtz_v4i1: 110; CHECK: @ %bb.0: @ %entry 111; CHECK-NEXT: vpt.i32 ne, q0, zr 112; CHECK-NEXT: vcmpt.i32 eq, q1, zr 113; CHECK-NEXT: vpsel q0, q1, q0 114; CHECK-NEXT: bx lr 115entry: 116 %c1 = icmp eq <4 x i32> %a, zeroinitializer 117 %c2 = icmp ugt <4 x i32> %b, zeroinitializer 118 %o = or <4 x i1> %c1, %c2 119 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 120 ret <4 x i32> %s 121} 122 123define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) { 124; CHECK-LABEL: cmpulez_v4i1: 125; CHECK: @ %bb.0: @ %entry 126; CHECK-NEXT: vcmp.u32 cs, q1, zr 127; CHECK-NEXT: vpnot 128; CHECK-NEXT: vpst 129; CHECK-NEXT: vcmpt.i32 ne, q0, zr 130; CHECK-NEXT: vpsel q0, q1, q0 131; CHECK-NEXT: bx lr 132entry: 133 %c1 = icmp eq <4 x i32> %a, zeroinitializer 134 %c2 = icmp ule <4 x i32> %b, zeroinitializer 135 %o = or <4 x i1> %c1, %c2 136 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 137 ret <4 x i32> %s 138} 139 140define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) { 141; CHECK-LABEL: cmpugez_v4i1: 142; CHECK: @ %bb.0: @ %entry 143; CHECK-NEXT: bx lr 144entry: 145 %c1 = icmp eq <4 x i32> %a, zeroinitializer 146 %c2 = icmp uge <4 x i32> %b, zeroinitializer 147 %o = or <4 x i1> %c1, %c2 148 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 149 ret <4 x i32> %s 150} 151 152 153 154define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 155; CHECK-LABEL: cmpeq_v4i1: 156; CHECK: @ %bb.0: @ %entry 157; CHECK-NEXT: vpt.i32 ne, q0, zr 158; CHECK-NEXT: vcmpt.i32 ne, q1, q2 159; CHECK-NEXT: vpsel q0, q1, q0 160; CHECK-NEXT: bx lr 161entry: 162 %c1 = icmp eq <4 x i32> %a, zeroinitializer 163 %c2 = icmp eq <4 x i32> %b, %c 164 %o = or <4 x i1> %c1, %c2 165 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 166 ret <4 x i32> %s 167} 168 169define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 170; CHECK-LABEL: cmpne_v4i1: 171; CHECK: @ %bb.0: @ %entry 172; CHECK-NEXT: vpt.i32 ne, q0, zr 173; CHECK-NEXT: vcmpt.i32 eq, q1, q2 174; CHECK-NEXT: vpsel q0, q1, q0 175; CHECK-NEXT: bx lr 176entry: 177 %c1 = icmp eq <4 x i32> %a, zeroinitializer 178 %c2 = icmp ne <4 x i32> %b, %c 179 %o = or <4 x i1> %c1, %c2 180 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 181 ret <4 x i32> %s 182} 183 184define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 185; CHECK-LABEL: cmpslt_v4i1: 186; CHECK: @ %bb.0: @ %entry 187; CHECK-NEXT: vpt.i32 ne, q0, zr 188; CHECK-NEXT: vcmpt.s32 le, q2, q1 189; CHECK-NEXT: vpsel q0, q1, q0 190; CHECK-NEXT: bx lr 191entry: 192 %c1 = icmp eq <4 x i32> %a, zeroinitializer 193 %c2 = icmp slt <4 x i32> %b, %c 194 %o = or <4 x i1> %c1, %c2 195 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 196 ret <4 x i32> %s 197} 198 199define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 200; CHECK-LABEL: cmpsgt_v4i1: 201; CHECK: @ %bb.0: @ %entry 202; CHECK-NEXT: vpt.i32 ne, q0, zr 203; CHECK-NEXT: vcmpt.s32 le, q1, q2 204; CHECK-NEXT: vpsel q0, q1, q0 205; CHECK-NEXT: bx lr 206entry: 207 %c1 = icmp eq <4 x i32> %a, zeroinitializer 208 %c2 = icmp sgt <4 x i32> %b, %c 209 %o = or <4 x i1> %c1, %c2 210 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 211 ret <4 x i32> %s 212} 213 214define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 215; CHECK-LABEL: cmpsle_v4i1: 216; CHECK: @ %bb.0: @ %entry 217; CHECK-NEXT: vpt.i32 ne, q0, zr 218; CHECK-NEXT: vcmpt.s32 lt, q2, q1 219; CHECK-NEXT: vpsel q0, q1, q0 220; CHECK-NEXT: bx lr 221entry: 222 %c1 = icmp eq <4 x i32> %a, zeroinitializer 223 %c2 = icmp sle <4 x i32> %b, %c 224 %o = or <4 x i1> %c1, %c2 225 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 226 ret <4 x i32> %s 227} 228 229define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 230; CHECK-LABEL: cmpsge_v4i1: 231; CHECK: @ %bb.0: @ %entry 232; CHECK-NEXT: vpt.i32 ne, q0, zr 233; CHECK-NEXT: vcmpt.s32 lt, q1, q2 234; CHECK-NEXT: vpsel q0, q1, q0 235; CHECK-NEXT: bx lr 236entry: 237 %c1 = icmp eq <4 x i32> %a, zeroinitializer 238 %c2 = icmp sge <4 x i32> %b, %c 239 %o = or <4 x i1> %c1, %c2 240 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 241 ret <4 x i32> %s 242} 243 244define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 245; CHECK-LABEL: cmpult_v4i1: 246; CHECK: @ %bb.0: @ %entry 247; CHECK-NEXT: vcmp.u32 hi, q2, q1 248; CHECK-NEXT: vpnot 249; CHECK-NEXT: vpst 250; CHECK-NEXT: vcmpt.i32 ne, q0, zr 251; CHECK-NEXT: vpsel q0, q1, q0 252; CHECK-NEXT: bx lr 253entry: 254 %c1 = icmp eq <4 x i32> %a, zeroinitializer 255 %c2 = icmp ult <4 x i32> %b, %c 256 %o = or <4 x i1> %c1, %c2 257 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 258 ret <4 x i32> %s 259} 260 261define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 262; CHECK-LABEL: cmpugt_v4i1: 263; CHECK: @ %bb.0: @ %entry 264; CHECK-NEXT: vcmp.u32 hi, q1, q2 265; CHECK-NEXT: vpnot 266; CHECK-NEXT: vpst 267; CHECK-NEXT: vcmpt.i32 ne, q0, zr 268; CHECK-NEXT: vpsel q0, q1, q0 269; CHECK-NEXT: bx lr 270entry: 271 %c1 = icmp eq <4 x i32> %a, zeroinitializer 272 %c2 = icmp ugt <4 x i32> %b, %c 273 %o = or <4 x i1> %c1, %c2 274 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 275 ret <4 x i32> %s 276} 277 278define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 279; CHECK-LABEL: cmpule_v4i1: 280; CHECK: @ %bb.0: @ %entry 281; CHECK-NEXT: vcmp.u32 cs, q2, q1 282; CHECK-NEXT: vpnot 283; CHECK-NEXT: vpst 284; CHECK-NEXT: vcmpt.i32 ne, q0, zr 285; CHECK-NEXT: vpsel q0, q1, q0 286; CHECK-NEXT: bx lr 287entry: 288 %c1 = icmp eq <4 x i32> %a, zeroinitializer 289 %c2 = icmp ule <4 x i32> %b, %c 290 %o = or <4 x i1> %c1, %c2 291 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 292 ret <4 x i32> %s 293} 294 295define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 296; CHECK-LABEL: cmpuge_v4i1: 297; CHECK: @ %bb.0: @ %entry 298; CHECK-NEXT: vcmp.u32 cs, q1, q2 299; CHECK-NEXT: vpnot 300; CHECK-NEXT: vpst 301; CHECK-NEXT: vcmpt.i32 ne, q0, zr 302; CHECK-NEXT: vpsel q0, q1, q0 303; CHECK-NEXT: bx lr 304entry: 305 %c1 = icmp eq <4 x i32> %a, zeroinitializer 306 %c2 = icmp uge <4 x i32> %b, %c 307 %o = or <4 x i1> %c1, %c2 308 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 309 ret <4 x i32> %s 310} 311 312 313 314 315define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) { 316; CHECK-LABEL: cmpeqz_v8i1: 317; CHECK: @ %bb.0: @ %entry 318; CHECK-NEXT: vpt.i16 ne, q0, zr 319; CHECK-NEXT: vcmpt.i16 ne, q1, zr 320; CHECK-NEXT: vpsel q0, q1, q0 321; CHECK-NEXT: bx lr 322entry: 323 %c1 = icmp eq <8 x i16> %a, zeroinitializer 324 %c2 = icmp eq <8 x i16> %b, zeroinitializer 325 %o = or <8 x i1> %c1, %c2 326 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b 327 ret <8 x i16> %s 328} 329 330define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 331; CHECK-LABEL: cmpeq_v8i1: 332; CHECK: @ %bb.0: @ %entry 333; CHECK-NEXT: vpt.i16 ne, q0, zr 334; CHECK-NEXT: vcmpt.i16 ne, q1, q2 335; CHECK-NEXT: vpsel q0, q1, q0 336; CHECK-NEXT: bx lr 337entry: 338 %c1 = icmp eq <8 x i16> %a, zeroinitializer 339 %c2 = icmp eq <8 x i16> %b, %c 340 %o = or <8 x i1> %c1, %c2 341 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b 342 ret <8 x i16> %s 343} 344 345 346define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) { 347; CHECK-LABEL: cmpeqz_v16i1: 348; CHECK: @ %bb.0: @ %entry 349; CHECK-NEXT: vpt.i8 ne, q0, zr 350; CHECK-NEXT: vcmpt.i8 ne, q1, zr 351; CHECK-NEXT: vpsel q0, q1, q0 352; CHECK-NEXT: bx lr 353entry: 354 %c1 = icmp eq <16 x i8> %a, zeroinitializer 355 %c2 = icmp eq <16 x i8> %b, zeroinitializer 356 %o = or <16 x i1> %c1, %c2 357 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b 358 ret <16 x i8> %s 359} 360 361define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 362; CHECK-LABEL: cmpeq_v16i1: 363; CHECK: @ %bb.0: @ %entry 364; CHECK-NEXT: vpt.i8 ne, q0, zr 365; CHECK-NEXT: vcmpt.i8 ne, q1, q2 366; CHECK-NEXT: vpsel q0, q1, q0 367; CHECK-NEXT: bx lr 368entry: 369 %c1 = icmp eq <16 x i8> %a, zeroinitializer 370 %c2 = icmp eq <16 x i8> %b, %c 371 %o = or <16 x i1> %c1, %c2 372 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b 373 ret <16 x i8> %s 374} 375 376 377define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) { 378; CHECK-LABEL: cmpeqz_v2i1: 379; CHECK: @ %bb.0: @ %entry 380; CHECK-NEXT: vmov r0, s5 381; CHECK-NEXT: vmov r1, s4 382; CHECK-NEXT: orrs r0, r1 383; CHECK-NEXT: vmov r1, s6 384; CHECK-NEXT: cset r0, eq 385; CHECK-NEXT: tst.w r0, #1 386; CHECK-NEXT: csetm r0, ne 387; CHECK-NEXT: vmov.32 q2[0], r0 388; CHECK-NEXT: vmov.32 q2[1], r0 389; CHECK-NEXT: vmov r0, s7 390; CHECK-NEXT: orrs r0, r1 391; CHECK-NEXT: vmov r1, s0 392; CHECK-NEXT: cset r0, eq 393; CHECK-NEXT: tst.w r0, #1 394; CHECK-NEXT: csetm r0, ne 395; CHECK-NEXT: vmov.32 q2[2], r0 396; CHECK-NEXT: vmov.32 q2[3], r0 397; CHECK-NEXT: vmov r0, s1 398; CHECK-NEXT: orrs r0, r1 399; CHECK-NEXT: vmov r1, s2 400; CHECK-NEXT: cset r0, eq 401; CHECK-NEXT: tst.w r0, #1 402; CHECK-NEXT: csetm r0, ne 403; CHECK-NEXT: vmov.32 q3[0], r0 404; CHECK-NEXT: vmov.32 q3[1], r0 405; CHECK-NEXT: vmov r0, s3 406; CHECK-NEXT: orrs r0, r1 407; CHECK-NEXT: cset r0, eq 408; CHECK-NEXT: tst.w r0, #1 409; CHECK-NEXT: csetm r0, ne 410; CHECK-NEXT: vmov.32 q3[2], r0 411; CHECK-NEXT: vmov.32 q3[3], r0 412; CHECK-NEXT: vorr q2, q3, q2 413; CHECK-NEXT: vbic q1, q1, q2 414; CHECK-NEXT: vand q0, q0, q2 415; CHECK-NEXT: vorr q0, q0, q1 416; CHECK-NEXT: bx lr 417entry: 418 %c1 = icmp eq <2 x i64> %a, zeroinitializer 419 %c2 = icmp eq <2 x i64> %b, zeroinitializer 420 %o = or <2 x i1> %c1, %c2 421 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b 422 ret <2 x i64> %s 423} 424 425define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 426; CHECK-LABEL: cmpeq_v2i1: 427; CHECK: @ %bb.0: @ %entry 428; CHECK-NEXT: vmov r0, s9 429; CHECK-NEXT: vmov r1, s5 430; CHECK-NEXT: vmov r2, s4 431; CHECK-NEXT: eors r0, r1 432; CHECK-NEXT: vmov r1, s8 433; CHECK-NEXT: eors r1, r2 434; CHECK-NEXT: vmov r2, s6 435; CHECK-NEXT: orrs r0, r1 436; CHECK-NEXT: vmov r1, s7 437; CHECK-NEXT: cset r0, eq 438; CHECK-NEXT: tst.w r0, #1 439; CHECK-NEXT: csetm r0, ne 440; CHECK-NEXT: vmov.32 q3[0], r0 441; CHECK-NEXT: vmov.32 q3[1], r0 442; CHECK-NEXT: vmov r0, s11 443; CHECK-NEXT: eors r0, r1 444; CHECK-NEXT: vmov r1, s10 445; CHECK-NEXT: eors r1, r2 446; CHECK-NEXT: orrs r0, r1 447; CHECK-NEXT: vmov r1, s0 448; CHECK-NEXT: cset r0, eq 449; CHECK-NEXT: tst.w r0, #1 450; CHECK-NEXT: csetm r0, ne 451; CHECK-NEXT: vmov.32 q3[2], r0 452; CHECK-NEXT: vmov.32 q3[3], r0 453; CHECK-NEXT: vmov r0, s1 454; CHECK-NEXT: orrs r0, r1 455; CHECK-NEXT: vmov r1, s2 456; CHECK-NEXT: cset r0, eq 457; CHECK-NEXT: tst.w r0, #1 458; CHECK-NEXT: csetm r0, ne 459; CHECK-NEXT: vmov.32 q2[0], r0 460; CHECK-NEXT: vmov.32 q2[1], r0 461; CHECK-NEXT: vmov r0, s3 462; CHECK-NEXT: orrs r0, r1 463; CHECK-NEXT: cset r0, eq 464; CHECK-NEXT: tst.w r0, #1 465; CHECK-NEXT: csetm r0, ne 466; CHECK-NEXT: vmov.32 q2[2], r0 467; CHECK-NEXT: vmov.32 q2[3], r0 468; CHECK-NEXT: vorr q2, q2, q3 469; CHECK-NEXT: vbic q1, q1, q2 470; CHECK-NEXT: vand q0, q0, q2 471; CHECK-NEXT: vorr q0, q0, q1 472; CHECK-NEXT: bx lr 473entry: 474 %c1 = icmp eq <2 x i64> %a, zeroinitializer 475 %c2 = icmp eq <2 x i64> %b, %c 476 %o = or <2 x i1> %c1, %c2 477 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b 478 ret <2 x i64> %s 479} 480 481 482