1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <16 x i8> @vpsel_i8(<16 x i8> %mask, <16 x i8> %src1, <16 x i8> %src2) {
5; CHECK-LABEL: vpsel_i8:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vcmp.i8 ne, q0, zr
8; CHECK-NEXT:    vpsel q0, q1, q2
9; CHECK-NEXT:    bx lr
10entry:
11  %0 = icmp ne <16 x i8> %mask, zeroinitializer
12  %1 = select <16 x i1> %0, <16 x i8> %src1, <16 x i8> %src2
13  ret <16 x i8> %1
14}
15
16define arm_aapcs_vfpcc <8 x i16> @vpsel_i16(<8 x i16> %mask, <8 x i16> %src1, <8 x i16> %src2) {
17; CHECK-LABEL: vpsel_i16:
18; CHECK:       @ %bb.0: @ %entry
19; CHECK-NEXT:    vcmp.i16 ne, q0, zr
20; CHECK-NEXT:    vpsel q0, q1, q2
21; CHECK-NEXT:    bx lr
22entry:
23  %0 = icmp ne <8 x i16> %mask, zeroinitializer
24  %1 = select <8 x i1> %0, <8 x i16> %src1, <8 x i16> %src2
25  ret <8 x i16> %1
26}
27
28define arm_aapcs_vfpcc <4 x i32> @vpsel_i32(<4 x i32> %mask, <4 x i32> %src1, <4 x i32> %src2) {
29; CHECK-LABEL: vpsel_i32:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vcmp.i32 ne, q0, zr
32; CHECK-NEXT:    vpsel q0, q1, q2
33; CHECK-NEXT:    bx lr
34entry:
35  %0 = icmp ne <4 x i32> %mask, zeroinitializer
36  %1 = select <4 x i1> %0, <4 x i32> %src1, <4 x i32> %src2
37  ret <4 x i32> %1
38}
39
40define arm_aapcs_vfpcc <8 x half> @vpsel_f16(<8 x i16> %mask, <8 x half> %src1, <8 x half> %src2) {
41; CHECK-LABEL: vpsel_f16:
42; CHECK:       @ %bb.0: @ %entry
43; CHECK-NEXT:    vcmp.i16 ne, q0, zr
44; CHECK-NEXT:    vpsel q0, q1, q2
45; CHECK-NEXT:    bx lr
46entry:
47  %0 = icmp ne <8 x i16> %mask, zeroinitializer
48  %1 = select <8 x i1> %0, <8 x half> %src1, <8 x half> %src2
49  ret <8 x half> %1
50}
51
52define arm_aapcs_vfpcc <4 x float> @vpsel_f32(<4 x i32> %mask, <4 x float> %src1, <4 x float> %src2) {
53; CHECK-LABEL: vpsel_f32:
54; CHECK:       @ %bb.0: @ %entry
55; CHECK-NEXT:    vcmp.i32 ne, q0, zr
56; CHECK-NEXT:    vpsel q0, q1, q2
57; CHECK-NEXT:    bx lr
58entry:
59  %0 = icmp ne <4 x i32> %mask, zeroinitializer
60  %1 = select <4 x i1> %0, <4 x float> %src1, <4 x float> %src2
61  ret <4 x float> %1
62}
63
64define arm_aapcs_vfpcc <4 x i32> @foo(<4 x i32> %vec.ind) {
65; CHECK-LABEL: foo:
66; CHECK:       @ %bb.0:
67; CHECK-NEXT:    vmov.i32 q2, #0x1
68; CHECK-NEXT:    vmov.i32 q1, #0x0
69; CHECK-NEXT:    vand q2, q0, q2
70; CHECK-NEXT:    vcmp.i32 eq, q2, zr
71; CHECK-NEXT:    vpsel q0, q0, q1
72; CHECK-NEXT:    bx lr
73  %tmp = and <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1>
74  %tmp1 = icmp eq <4 x i32> %tmp, zeroinitializer
75  %tmp2 = select <4 x i1> %tmp1, <4 x i32> %vec.ind, <4 x i32> zeroinitializer
76  ret <4 x i32> %tmp2
77}
78