1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6  target triple = "thumbv8.1m.main-none-none-eabi"
7
8  define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_2_preds(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 {
9  entry:
10    %conv.i = zext i16 %p1 to i32
11    %0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12    %conv.i5 = zext i16 %p2 to i32
13    %1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %0, <4 x float> %b, i32 %conv.i5) #2
14    ret <4 x float> %1
15  }
16
17  declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
18
19  attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
20  attributes #1 = { nounwind readnone }
21  attributes #2 = { nounwind }
22
23...
24---
25name:            vpt_2_blocks_2_preds
26alignment:       4
27exposesReturnsTwice: false
28legalized:       false
29regBankSelected: false
30selected:        false
31failedISel:      false
32tracksRegLiveness: true
33hasWinCFI:       false
34registers:       []
35liveins:
36  - { reg: '$q0', virtual-reg: '' }
37  - { reg: '$q1', virtual-reg: '' }
38  - { reg: '$q2', virtual-reg: '' }
39  - { reg: '$r0', virtual-reg: '' }
40  - { reg: '$r1', virtual-reg: '' }
41frameInfo:
42  isFrameAddressTaken: false
43  isReturnAddressTaken: false
44  hasStackMap:     false
45  hasPatchPoint:   false
46  stackSize:       0
47  offsetAdjustment: 0
48  maxAlignment:    0
49  adjustsStack:    false
50  hasCalls:        false
51  stackProtector:  ''
52  maxCallFrameSize: 0
53  cvBytesOfCalleeSavedRegisters: 0
54  hasOpaqueSPAdjustment: false
55  hasVAStart:      false
56  hasMustTailInVarArgFunc: false
57  localFrameSize:  0
58  savePoint:       ''
59  restorePoint:    ''
60fixedStack:      []
61stack:           []
62constants:       []
63body:             |
64  bb.0.entry:
65    liveins: $q0, $q1, $q2, $r0, $r1
66
67    ; CHECK-LABEL: name: vpt_2_blocks_2_preds
68    ; CHECK: liveins: $q0, $q1, $q2, $r0, $r1
69    ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
70    ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
71    ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
72    ; CHECK:   MVE_VPST 8, implicit $vpr
73    ; CHECK:   renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3
74    ; CHECK: }
75    ; CHECK: $vpr = VMSR_P0 killed $r1, 14 /* CC::al */, $noreg
76    ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q3, implicit killed $q2, implicit killed $q0 {
77    ; CHECK:   MVE_VPST 8, implicit $vpr
78    ; CHECK:   renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
79    ; CHECK: }
80    ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
81    $vpr = VMSR_P0 killed $r0, 14, $noreg
82    $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
83    renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3
84    $vpr = VMSR_P0 killed $r1, 14, $noreg
85    renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
86    tBX_RET 14, $noreg, implicit $q0
87
88...
89