1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6  target triple = "thumbv8.1m.main-none-none-eabi"
7
8  define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_ctrl_flow(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9  entry:
10    %conv.i = zext i16 %p to i32
11    %0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12    %1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
13    br label %bb2
14  bb2:
15    %2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
16    %3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
17    ret <4 x float> %3
18  }
19
20  declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
21
22  attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
23  attributes #1 = { nounwind readnone }
24  attributes #2 = { nounwind }
25
26...
27---
28name:            vpt_2_blocks_ctrl_flow
29alignment:       4
30exposesReturnsTwice: false
31legalized:       false
32regBankSelected: false
33selected:        false
34failedISel:      false
35tracksRegLiveness: true
36hasWinCFI:       false
37registers:       []
38liveins:
39  - { reg: '$q0', virtual-reg: '' }
40  - { reg: '$q1', virtual-reg: '' }
41  - { reg: '$q2', virtual-reg: '' }
42  - { reg: '$r0', virtual-reg: '' }
43frameInfo:
44  isFrameAddressTaken: false
45  isReturnAddressTaken: false
46  hasStackMap:     false
47  hasPatchPoint:   false
48  stackSize:       0
49  offsetAdjustment: 0
50  maxAlignment:    0
51  adjustsStack:    false
52  hasCalls:        false
53  stackProtector:  ''
54  maxCallFrameSize: 0
55  cvBytesOfCalleeSavedRegisters: 0
56  hasOpaqueSPAdjustment: false
57  hasVAStart:      false
58  hasMustTailInVarArgFunc: false
59  localFrameSize:  0
60  savePoint:       ''
61  restorePoint:    ''
62fixedStack:      []
63stack:           []
64constants:       []
65body:             |
66  ; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow
67  ; CHECK: bb.0.entry:
68  ; CHECK:   successors: %bb.1(0x80000000)
69  ; CHECK:   liveins: $q0, $q1, $q2, $r0
70  ; CHECK:   $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
71  ; CHECK:   $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
72  ; CHECK:   BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
73  ; CHECK:     MVE_VPST 4, implicit $vpr
74  ; CHECK:     renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
75  ; CHECK:     renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1
76  ; CHECK:   }
77  ; CHECK: bb.1.bb2:
78  ; CHECK:   liveins: $q0, $q1, $q2, $q3, $vpr
79  ; CHECK:   BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
80  ; CHECK:     MVE_VPST 4, implicit $vpr
81  ; CHECK:     renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
82  ; CHECK:     renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
83  ; CHECK:   }
84  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $q0
85  bb.0.entry:
86    liveins: $q0, $q1, $q2, $r0
87
88    $vpr = VMSR_P0 killed $r0, 14, $noreg
89    $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
90    renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
91    renamable $q1 = nnan ninf nsz MVE_VMINNMf32 renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
92
93  bb.1.bb2:
94    liveins: $q0, $q1, $q2, $q3, $vpr
95
96    renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
97    renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
98    tBX_RET 14, $noreg, implicit $q0
99
100...
101