1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @vqmovni32_smaxmin(<4 x i32> %s0) {
5; CHECK-LABEL: vqmovni32_smaxmin:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vqmovnb.s32 q0, q0
8; CHECK-NEXT:    vmovlb.s16 q0, q0
9; CHECK-NEXT:    bx lr
10entry:
11  %c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>
12  %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
13  %c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
14  %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
15  ret <4 x i32> %s2
16}
17
18define arm_aapcs_vfpcc <4 x i32> @vqmovni32_sminmax(<4 x i32> %s0) {
19; CHECK-LABEL: vqmovni32_sminmax:
20; CHECK:       @ %bb.0: @ %entry
21; CHECK-NEXT:    vqmovnb.s32 q0, q0
22; CHECK-NEXT:    vmovlb.s16 q0, q0
23; CHECK-NEXT:    bx lr
24entry:
25  %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
26  %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
27  %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>
28  %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
29  ret <4 x i32> %s2
30}
31
32define arm_aapcs_vfpcc <4 x i32> @vqmovni32_umaxmin(<4 x i32> %s0) {
33; CHECK-LABEL: vqmovni32_umaxmin:
34; CHECK:       @ %bb.0: @ %entry
35; CHECK-NEXT:    vqmovnb.u32 q0, q0
36; CHECK-NEXT:    vmovlb.u16 q0, q0
37; CHECK-NEXT:    bx lr
38entry:
39  %c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
40  %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
41  ret <4 x i32> %s1
42}
43
44define arm_aapcs_vfpcc <4 x i32> @vqmovni32_uminmax(<4 x i32> %s0) {
45; CHECK-LABEL: vqmovni32_uminmax:
46; CHECK:       @ %bb.0: @ %entry
47; CHECK-NEXT:    vqmovnb.u32 q0, q0
48; CHECK-NEXT:    vmovlb.u16 q0, q0
49; CHECK-NEXT:    bx lr
50entry:
51  %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
52  %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
53  ret <4 x i32> %s2
54}
55
56define arm_aapcs_vfpcc <8 x i16> @vqmovni16_smaxmin(<8 x i16> %s0) {
57; CHECK-LABEL: vqmovni16_smaxmin:
58; CHECK:       @ %bb.0: @ %entry
59; CHECK-NEXT:    vqmovnb.s16 q0, q0
60; CHECK-NEXT:    vmovlb.s8 q0, q0
61; CHECK-NEXT:    bx lr
62entry:
63  %c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
64  %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
65  %c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
66  %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
67  ret <8 x i16> %s2
68}
69
70define arm_aapcs_vfpcc <8 x i16> @vqmovni16_sminmax(<8 x i16> %s0) {
71; CHECK-LABEL: vqmovni16_sminmax:
72; CHECK:       @ %bb.0: @ %entry
73; CHECK-NEXT:    vqmovnb.s16 q0, q0
74; CHECK-NEXT:    vmovlb.s8 q0, q0
75; CHECK-NEXT:    bx lr
76entry:
77  %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
78  %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
79  %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
80  %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
81  ret <8 x i16> %s2
82}
83
84define arm_aapcs_vfpcc <8 x i16> @vqmovni16_umaxmin(<8 x i16> %s0) {
85; CHECK-LABEL: vqmovni16_umaxmin:
86; CHECK:       @ %bb.0: @ %entry
87; CHECK-NEXT:    vqmovnb.u16 q0, q0
88; CHECK-NEXT:    vmovlb.u8 q0, q0
89; CHECK-NEXT:    bx lr
90entry:
91  %c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
92  %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
93  ret <8 x i16> %s1
94}
95
96define arm_aapcs_vfpcc <8 x i16> @vqmovni16_uminmax(<8 x i16> %s0) {
97; CHECK-LABEL: vqmovni16_uminmax:
98; CHECK:       @ %bb.0: @ %entry
99; CHECK-NEXT:    vqmovnb.u16 q0, q0
100; CHECK-NEXT:    vmovlb.u8 q0, q0
101; CHECK-NEXT:    bx lr
102entry:
103  %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
104  %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
105  ret <8 x i16> %s2
106}
107
108define arm_aapcs_vfpcc <16 x i8> @vqmovni8_smaxmin(<16 x i8> %s0) {
109; CHECK-LABEL: vqmovni8_smaxmin:
110; CHECK:       @ %bb.0: @ %entry
111; CHECK-NEXT:    vmov.i8 q1, #0x7
112; CHECK-NEXT:    vmin.s8 q0, q0, q1
113; CHECK-NEXT:    vmov.i8 q1, #0xf8
114; CHECK-NEXT:    vmax.s8 q0, q0, q1
115; CHECK-NEXT:    bx lr
116entry:
117  %c1 = icmp slt <16 x i8> %s0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
118  %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
119  %c2 = icmp sgt <16 x i8> %s1, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
120  %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
121  ret <16 x i8> %s2
122}
123
124define arm_aapcs_vfpcc <16 x i8> @vqmovni8_sminmax(<16 x i8> %s0) {
125; CHECK-LABEL: vqmovni8_sminmax:
126; CHECK:       @ %bb.0: @ %entry
127; CHECK-NEXT:    vmov.i8 q1, #0xf8
128; CHECK-NEXT:    vmax.s8 q0, q0, q1
129; CHECK-NEXT:    vmov.i8 q1, #0x7
130; CHECK-NEXT:    vmin.s8 q0, q0, q1
131; CHECK-NEXT:    bx lr
132entry:
133  %c1 = icmp sgt <16 x i8> %s0, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
134  %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
135  %c2 = icmp slt <16 x i8> %s1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
136  %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
137  ret <16 x i8> %s2
138}
139
140define arm_aapcs_vfpcc <16 x i8> @vqmovni8_umaxmin(<16 x i8> %s0) {
141; CHECK-LABEL: vqmovni8_umaxmin:
142; CHECK:       @ %bb.0: @ %entry
143; CHECK-NEXT:    vmov.i8 q1, #0xf
144; CHECK-NEXT:    vmin.u8 q0, q0, q1
145; CHECK-NEXT:    bx lr
146entry:
147  %c1 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
148  %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
149  ret <16 x i8> %s1
150}
151
152define arm_aapcs_vfpcc <16 x i8> @vqmovni8_uminmax(<16 x i8> %s0) {
153; CHECK-LABEL: vqmovni8_uminmax:
154; CHECK:       @ %bb.0: @ %entry
155; CHECK-NEXT:    vmov.i8 q1, #0xf
156; CHECK-NEXT:    vmin.u8 q0, q0, q1
157; CHECK-NEXT:    bx lr
158entry:
159  %c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
160  %s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
161  ret <16 x i8> %s2
162}
163
164define arm_aapcs_vfpcc <2 x i64> @vqmovni64_smaxmin(<2 x i64> %s0) {
165; CHECK-LABEL: vqmovni64_smaxmin:
166; CHECK:       @ %bb.0: @ %entry
167; CHECK-NEXT:    vmov r2, s0
168; CHECK-NEXT:    mvn r3, #-2147483648
169; CHECK-NEXT:    vmov r1, s1
170; CHECK-NEXT:    movs r0, #0
171; CHECK-NEXT:    subs r2, r2, r3
172; CHECK-NEXT:    sbcs r1, r1, #0
173; CHECK-NEXT:    vmov r2, s2
174; CHECK-NEXT:    mov.w r1, #0
175; CHECK-NEXT:    it lt
176; CHECK-NEXT:    movlt r1, #1
177; CHECK-NEXT:    cmp r1, #0
178; CHECK-NEXT:    csetm r1, ne
179; CHECK-NEXT:    vmov.32 q1[0], r1
180; CHECK-NEXT:    vmov.32 q1[1], r1
181; CHECK-NEXT:    vmov r1, s3
182; CHECK-NEXT:    subs r2, r2, r3
183; CHECK-NEXT:    mov.w r3, #-1
184; CHECK-NEXT:    sbcs r1, r1, #0
185; CHECK-NEXT:    mov.w r1, #0
186; CHECK-NEXT:    it lt
187; CHECK-NEXT:    movlt r1, #1
188; CHECK-NEXT:    cmp r1, #0
189; CHECK-NEXT:    csetm r1, ne
190; CHECK-NEXT:    vmov.32 q1[2], r1
191; CHECK-NEXT:    vmov.32 q1[3], r1
192; CHECK-NEXT:    adr r1, .LCPI12_0
193; CHECK-NEXT:    vldrw.u32 q2, [r1]
194; CHECK-NEXT:    vand q0, q0, q1
195; CHECK-NEXT:    vbic q2, q2, q1
196; CHECK-NEXT:    vorr q0, q0, q2
197; CHECK-NEXT:    vmov r2, s0
198; CHECK-NEXT:    vmov r1, s1
199; CHECK-NEXT:    rsbs.w r2, r2, #-2147483648
200; CHECK-NEXT:    sbcs.w r1, r3, r1
201; CHECK-NEXT:    vmov r2, s2
202; CHECK-NEXT:    mov.w r1, #0
203; CHECK-NEXT:    it lt
204; CHECK-NEXT:    movlt r1, #1
205; CHECK-NEXT:    cmp r1, #0
206; CHECK-NEXT:    csetm r1, ne
207; CHECK-NEXT:    vmov.32 q1[0], r1
208; CHECK-NEXT:    vmov.32 q1[1], r1
209; CHECK-NEXT:    vmov r1, s3
210; CHECK-NEXT:    rsbs.w r2, r2, #-2147483648
211; CHECK-NEXT:    sbcs.w r1, r3, r1
212; CHECK-NEXT:    it lt
213; CHECK-NEXT:    movlt r0, #1
214; CHECK-NEXT:    cmp r0, #0
215; CHECK-NEXT:    csetm r0, ne
216; CHECK-NEXT:    vmov.32 q1[2], r0
217; CHECK-NEXT:    vmov.32 q1[3], r0
218; CHECK-NEXT:    adr r0, .LCPI12_1
219; CHECK-NEXT:    vldrw.u32 q2, [r0]
220; CHECK-NEXT:    vand q0, q0, q1
221; CHECK-NEXT:    vbic q2, q2, q1
222; CHECK-NEXT:    vorr q0, q0, q2
223; CHECK-NEXT:    bx lr
224; CHECK-NEXT:    .p2align 4
225; CHECK-NEXT:  @ %bb.1:
226; CHECK-NEXT:  .LCPI12_0:
227; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
228; CHECK-NEXT:    .long 0 @ 0x0
229; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
230; CHECK-NEXT:    .long 0 @ 0x0
231; CHECK-NEXT:  .LCPI12_1:
232; CHECK-NEXT:    .long 2147483648 @ 0x80000000
233; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
234; CHECK-NEXT:    .long 2147483648 @ 0x80000000
235; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
236entry:
237  %c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>
238  %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>
239  %c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648>
240  %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648>
241  ret <2 x i64> %s2
242}
243
244define arm_aapcs_vfpcc <2 x i64> @vqmovni64_sminmax(<2 x i64> %s0) {
245; CHECK-LABEL: vqmovni64_sminmax:
246; CHECK:       @ %bb.0: @ %entry
247; CHECK-NEXT:    vmov r2, s0
248; CHECK-NEXT:    mov.w r3, #-1
249; CHECK-NEXT:    vmov r1, s1
250; CHECK-NEXT:    movs r0, #0
251; CHECK-NEXT:    rsbs.w r2, r2, #-2147483648
252; CHECK-NEXT:    sbcs.w r1, r3, r1
253; CHECK-NEXT:    vmov r2, s2
254; CHECK-NEXT:    mov.w r1, #0
255; CHECK-NEXT:    it lt
256; CHECK-NEXT:    movlt r1, #1
257; CHECK-NEXT:    cmp r1, #0
258; CHECK-NEXT:    csetm r1, ne
259; CHECK-NEXT:    vmov.32 q1[0], r1
260; CHECK-NEXT:    vmov.32 q1[1], r1
261; CHECK-NEXT:    vmov r1, s3
262; CHECK-NEXT:    rsbs.w r2, r2, #-2147483648
263; CHECK-NEXT:    sbcs.w r1, r3, r1
264; CHECK-NEXT:    mvn r3, #-2147483648
265; CHECK-NEXT:    mov.w r1, #0
266; CHECK-NEXT:    it lt
267; CHECK-NEXT:    movlt r1, #1
268; CHECK-NEXT:    cmp r1, #0
269; CHECK-NEXT:    csetm r1, ne
270; CHECK-NEXT:    vmov.32 q1[2], r1
271; CHECK-NEXT:    vmov.32 q1[3], r1
272; CHECK-NEXT:    adr r1, .LCPI13_0
273; CHECK-NEXT:    vldrw.u32 q2, [r1]
274; CHECK-NEXT:    vand q0, q0, q1
275; CHECK-NEXT:    vbic q2, q2, q1
276; CHECK-NEXT:    vorr q0, q0, q2
277; CHECK-NEXT:    vmov r2, s0
278; CHECK-NEXT:    vmov r1, s1
279; CHECK-NEXT:    subs r2, r2, r3
280; CHECK-NEXT:    sbcs r1, r1, #0
281; CHECK-NEXT:    vmov r2, s2
282; CHECK-NEXT:    mov.w r1, #0
283; CHECK-NEXT:    it lt
284; CHECK-NEXT:    movlt r1, #1
285; CHECK-NEXT:    cmp r1, #0
286; CHECK-NEXT:    csetm r1, ne
287; CHECK-NEXT:    vmov.32 q1[0], r1
288; CHECK-NEXT:    vmov.32 q1[1], r1
289; CHECK-NEXT:    vmov r1, s3
290; CHECK-NEXT:    subs r2, r2, r3
291; CHECK-NEXT:    sbcs r1, r1, #0
292; CHECK-NEXT:    it lt
293; CHECK-NEXT:    movlt r0, #1
294; CHECK-NEXT:    cmp r0, #0
295; CHECK-NEXT:    csetm r0, ne
296; CHECK-NEXT:    vmov.32 q1[2], r0
297; CHECK-NEXT:    vmov.32 q1[3], r0
298; CHECK-NEXT:    adr r0, .LCPI13_1
299; CHECK-NEXT:    vldrw.u32 q2, [r0]
300; CHECK-NEXT:    vand q0, q0, q1
301; CHECK-NEXT:    vbic q2, q2, q1
302; CHECK-NEXT:    vorr q0, q0, q2
303; CHECK-NEXT:    bx lr
304; CHECK-NEXT:    .p2align 4
305; CHECK-NEXT:  @ %bb.1:
306; CHECK-NEXT:  .LCPI13_0:
307; CHECK-NEXT:    .long 2147483648 @ 0x80000000
308; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
309; CHECK-NEXT:    .long 2147483648 @ 0x80000000
310; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
311; CHECK-NEXT:  .LCPI13_1:
312; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
313; CHECK-NEXT:    .long 0 @ 0x0
314; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
315; CHECK-NEXT:    .long 0 @ 0x0
316entry:
317  %c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>
318  %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>
319  %c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647>
320  %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647>
321  ret <2 x i64> %s2
322}
323
324define arm_aapcs_vfpcc <2 x i64> @vqmovni64_umaxmin(<2 x i64> %s0) {
325; CHECK-LABEL: vqmovni64_umaxmin:
326; CHECK:       @ %bb.0: @ %entry
327; CHECK-NEXT:    vmov r1, s0
328; CHECK-NEXT:    movs r2, #0
329; CHECK-NEXT:    vmov r0, s1
330; CHECK-NEXT:    vmov.i64 q2, #0xffffffff
331; CHECK-NEXT:    subs.w r1, r1, #-1
332; CHECK-NEXT:    sbcs r0, r0, #0
333; CHECK-NEXT:    vmov r1, s2
334; CHECK-NEXT:    mov.w r0, #0
335; CHECK-NEXT:    it lo
336; CHECK-NEXT:    movlo r0, #1
337; CHECK-NEXT:    cmp r0, #0
338; CHECK-NEXT:    csetm r0, ne
339; CHECK-NEXT:    vmov.32 q1[0], r0
340; CHECK-NEXT:    vmov.32 q1[1], r0
341; CHECK-NEXT:    vmov r0, s3
342; CHECK-NEXT:    subs.w r1, r1, #-1
343; CHECK-NEXT:    sbcs r0, r0, #0
344; CHECK-NEXT:    it lo
345; CHECK-NEXT:    movlo r2, #1
346; CHECK-NEXT:    cmp r2, #0
347; CHECK-NEXT:    csetm r0, ne
348; CHECK-NEXT:    vmov.32 q1[2], r0
349; CHECK-NEXT:    vmov.32 q1[3], r0
350; CHECK-NEXT:    vbic q2, q2, q1
351; CHECK-NEXT:    vand q0, q0, q1
352; CHECK-NEXT:    vorr q0, q0, q2
353; CHECK-NEXT:    bx lr
354entry:
355  %c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
356  %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
357  ret <2 x i64> %s1
358}
359
360define arm_aapcs_vfpcc <2 x i64> @vqmovni64_uminmax(<2 x i64> %s0) {
361; CHECK-LABEL: vqmovni64_uminmax:
362; CHECK:       @ %bb.0: @ %entry
363; CHECK-NEXT:    vmov r1, s0
364; CHECK-NEXT:    movs r2, #0
365; CHECK-NEXT:    vmov r0, s1
366; CHECK-NEXT:    vmov.i64 q2, #0xffffffff
367; CHECK-NEXT:    subs.w r1, r1, #-1
368; CHECK-NEXT:    sbcs r0, r0, #0
369; CHECK-NEXT:    vmov r1, s2
370; CHECK-NEXT:    mov.w r0, #0
371; CHECK-NEXT:    it lo
372; CHECK-NEXT:    movlo r0, #1
373; CHECK-NEXT:    cmp r0, #0
374; CHECK-NEXT:    csetm r0, ne
375; CHECK-NEXT:    vmov.32 q1[0], r0
376; CHECK-NEXT:    vmov.32 q1[1], r0
377; CHECK-NEXT:    vmov r0, s3
378; CHECK-NEXT:    subs.w r1, r1, #-1
379; CHECK-NEXT:    sbcs r0, r0, #0
380; CHECK-NEXT:    it lo
381; CHECK-NEXT:    movlo r2, #1
382; CHECK-NEXT:    cmp r2, #0
383; CHECK-NEXT:    csetm r0, ne
384; CHECK-NEXT:    vmov.32 q1[2], r0
385; CHECK-NEXT:    vmov.32 q1[3], r0
386; CHECK-NEXT:    vbic q2, q2, q1
387; CHECK-NEXT:    vand q0, q0, q1
388; CHECK-NEXT:    vorr q0, q0, q2
389; CHECK-NEXT:    bx lr
390entry:
391  %c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
392  %s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
393  ret <2 x i64> %s2
394}
395