1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s 3 4--- | 5 define i32* @t2LDRi12(i32* %x, i32 %y) { unreachable } 6 define i32* @t2LDRHi12(i32* %x, i32 %y) { unreachable } 7 define i32* @t2LDRSHi12(i32* %x, i32 %y) { unreachable } 8 define i32* @t2LDRBi12(i32* %x, i32 %y) { unreachable } 9 define i32* @t2LDRSBi12(i32* %x, i32 %y) { unreachable } 10 define i32* @t2STRi12(i32* %x, i32 %y) { unreachable } 11 define i32* @t2STRHi12(i32* %x, i32 %y) { unreachable } 12 define i32* @t2STRBi12(i32* %x, i32 %y) { unreachable } 13 14 define i32* @storedadd(i32* %x, i32 %y) { unreachable } 15 define i32* @minsize2(i32* %x, i32 %y) minsize optsize { unreachable } 16 define i32* @minsize3(i32* %x, i32 %y) minsize optsize { unreachable } 17 18... 19--- 20name: t2LDRi12 21tracksRegLiveness: true 22registers: 23 - { id: 0, class: gprnopc, preferred-register: '' } 24 - { id: 1, class: rgpr, preferred-register: '' } 25 - { id: 2, class: rgpr, preferred-register: '' } 26liveins: 27 - { reg: '$r0', virtual-reg: '%0' } 28body: | 29 bb.0: 30 liveins: $r0 31 32 ; CHECK-LABEL: name: t2LDRi12 33 ; CHECK: liveins: $r0 34 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 35 ; CHECK: [[t2LDRi12_:%[0-9]+]]:rgpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4) 36 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 37 ; CHECK: $r0 = COPY [[t2ADDri]] 38 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 39 %0:gprnopc = COPY $r0 40 %1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load 4, align 4) 41 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 42 $r0 = COPY %2 43 tBX_RET 14, $noreg, implicit $r0 44 45... 46--- 47name: t2LDRHi12 48tracksRegLiveness: true 49registers: 50 - { id: 0, class: gprnopc, preferred-register: '' } 51 - { id: 1, class: rgpr, preferred-register: '' } 52 - { id: 2, class: rgpr, preferred-register: '' } 53liveins: 54 - { reg: '$r0', virtual-reg: '%0' } 55body: | 56 bb.0: 57 liveins: $r0 58 59 ; CHECK-LABEL: name: t2LDRHi12 60 ; CHECK: liveins: $r0 61 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 62 ; CHECK: [[t2LDRH_POST:%[0-9]+]]:rgpr, [[t2LDRH_POST1:%[0-9]+]]:rgpr = t2LDRH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load 4) 63 ; CHECK: $r0 = COPY [[t2LDRH_POST1]] 64 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 65 %0:gprnopc = COPY $r0 66 %1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load 4, align 4) 67 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 68 $r0 = COPY %2 69 tBX_RET 14, $noreg, implicit $r0 70 71... 72--- 73name: t2LDRSHi12 74tracksRegLiveness: true 75registers: 76 - { id: 0, class: gprnopc, preferred-register: '' } 77 - { id: 1, class: rgpr, preferred-register: '' } 78 - { id: 2, class: rgpr, preferred-register: '' } 79liveins: 80 - { reg: '$r0', virtual-reg: '%0' } 81body: | 82 bb.0: 83 liveins: $r0 84 85 ; CHECK-LABEL: name: t2LDRSHi12 86 ; CHECK: liveins: $r0 87 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 88 ; CHECK: [[t2LDRSH_POST:%[0-9]+]]:rgpr, [[t2LDRSH_POST1:%[0-9]+]]:rgpr = t2LDRSH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load 4) 89 ; CHECK: $r0 = COPY [[t2LDRSH_POST1]] 90 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 91 %0:gprnopc = COPY $r0 92 %1:rgpr = t2LDRSHi12 %0, 0, 14, $noreg :: (load 4, align 4) 93 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 94 $r0 = COPY %2 95 tBX_RET 14, $noreg, implicit $r0 96 97... 98--- 99name: t2LDRBi12 100tracksRegLiveness: true 101registers: 102 - { id: 0, class: gprnopc, preferred-register: '' } 103 - { id: 1, class: rgpr, preferred-register: '' } 104 - { id: 2, class: rgpr, preferred-register: '' } 105liveins: 106 - { reg: '$r0', virtual-reg: '%0' } 107body: | 108 bb.0: 109 liveins: $r0 110 111 ; CHECK-LABEL: name: t2LDRBi12 112 ; CHECK: liveins: $r0 113 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 114 ; CHECK: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load 4) 115 ; CHECK: $r0 = COPY [[t2LDRB_POST1]] 116 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 117 %0:gprnopc = COPY $r0 118 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load 4, align 4) 119 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 120 $r0 = COPY %2 121 tBX_RET 14, $noreg, implicit $r0 122 123... 124--- 125name: t2LDRSBi12 126tracksRegLiveness: true 127registers: 128 - { id: 0, class: gprnopc, preferred-register: '' } 129 - { id: 1, class: rgpr, preferred-register: '' } 130 - { id: 2, class: rgpr, preferred-register: '' } 131liveins: 132 - { reg: '$r0', virtual-reg: '%0' } 133body: | 134 bb.0: 135 liveins: $r0 136 137 ; CHECK-LABEL: name: t2LDRSBi12 138 ; CHECK: liveins: $r0 139 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 140 ; CHECK: [[t2LDRSB_POST:%[0-9]+]]:rgpr, [[t2LDRSB_POST1:%[0-9]+]]:rgpr = t2LDRSB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load 4) 141 ; CHECK: $r0 = COPY [[t2LDRSB_POST1]] 142 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 143 %0:gprnopc = COPY $r0 144 %1:rgpr = t2LDRSBi12 %0, 0, 14, $noreg :: (load 4, align 4) 145 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 146 $r0 = COPY %2 147 tBX_RET 14, $noreg, implicit $r0 148 149... 150--- 151name: t2STRi12 152tracksRegLiveness: true 153registers: 154 - { id: 0, class: gprnopc, preferred-register: '' } 155 - { id: 1, class: rgpr, preferred-register: '' } 156 - { id: 2, class: rgpr, preferred-register: '' } 157liveins: 158 - { reg: '$r0', virtual-reg: '%0' } 159 - { reg: '$r1', virtual-reg: '%1' } 160body: | 161 bb.0: 162 liveins: $r0, $r1 163 164 ; CHECK-LABEL: name: t2STRi12 165 ; CHECK: liveins: $r0, $r1 166 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 167 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 168 ; CHECK: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4) 169 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 170 ; CHECK: $r0 = COPY [[t2ADDri]] 171 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 172 %0:gprnopc = COPY $r0 173 %1:rgpr = COPY $r1 174 t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store 4, align 4) 175 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 176 $r0 = COPY %2 177 tBX_RET 14, $noreg, implicit $r0 178 179... 180--- 181name: t2STRHi12 182tracksRegLiveness: true 183registers: 184 - { id: 0, class: gprnopc, preferred-register: '' } 185 - { id: 1, class: rgpr, preferred-register: '' } 186 - { id: 2, class: rgpr, preferred-register: '' } 187liveins: 188 - { reg: '$r0', virtual-reg: '%0' } 189 - { reg: '$r1', virtual-reg: '%1' } 190body: | 191 bb.0: 192 liveins: $r0, $r1 193 194 ; CHECK-LABEL: name: t2STRHi12 195 ; CHECK: liveins: $r0, $r1 196 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 197 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 198 ; CHECK: early-clobber %2:rgpr = t2STRH_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store 4) 199 ; CHECK: $r0 = COPY %2 200 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 201 %0:gprnopc = COPY $r0 202 %1:rgpr = COPY $r1 203 t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store 4, align 4) 204 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 205 $r0 = COPY %2 206 tBX_RET 14, $noreg, implicit $r0 207 208... 209--- 210name: t2STRBi12 211tracksRegLiveness: true 212registers: 213 - { id: 0, class: gprnopc, preferred-register: '' } 214 - { id: 1, class: rgpr, preferred-register: '' } 215 - { id: 2, class: rgpr, preferred-register: '' } 216liveins: 217 - { reg: '$r0', virtual-reg: '%0' } 218 - { reg: '$r1', virtual-reg: '%1' } 219body: | 220 bb.0: 221 liveins: $r0, $r1 222 223 ; CHECK-LABEL: name: t2STRBi12 224 ; CHECK: liveins: $r0, $r1 225 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 226 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 227 ; CHECK: early-clobber %2:rgpr = t2STRB_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store 4) 228 ; CHECK: $r0 = COPY %2 229 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 230 %0:gprnopc = COPY $r0 231 %1:rgpr = COPY $r1 232 t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store 4, align 4) 233 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 234 $r0 = COPY %2 235 tBX_RET 14, $noreg, implicit $r0 236 237... 238--- 239name: storedadd 240tracksRegLiveness: true 241registers: 242 - { id: 0, class: gprnopc, preferred-register: '' } 243 - { id: 1, class: rgpr, preferred-register: '' } 244liveins: 245 - { reg: '$r0', virtual-reg: '%0' } 246body: | 247 bb.0: 248 liveins: $r0 249 250 ; CHECK-LABEL: name: storedadd 251 ; CHECK: liveins: $r0 252 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 253 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 254 ; CHECK: t2STRi12 [[t2ADDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4) 255 ; CHECK: $r0 = COPY [[t2ADDri]] 256 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 257 %0:gprnopc = COPY $r0 258 %1:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 259 t2STRi12 %1, %0, 0, 14, $noreg :: (store 4, align 4) 260 $r0 = COPY %1 261 tBX_RET 14, $noreg, implicit $r0 262 263... 264--- 265name: minsize2 266tracksRegLiveness: true 267registers: 268 - { id: 0, class: gprnopc, preferred-register: '' } 269 - { id: 1, class: rgpr, preferred-register: '' } 270 - { id: 2, class: rgpr, preferred-register: '' } 271 - { id: 3, class: rgpr, preferred-register: '' } 272liveins: 273 - { reg: '$r0', virtual-reg: '%0' } 274body: | 275 bb.0: 276 liveins: $r0 277 278 ; CHECK-LABEL: name: minsize2 279 ; CHECK: liveins: $r0 280 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 281 ; CHECK: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load 4) 282 ; CHECK: [[t2LDRBi8_:%[0-9]+]]:rgpr = t2LDRBi8 [[t2LDRB_POST1]], -30, 14 /* CC::al */, $noreg :: (load 4) 283 ; CHECK: $r0 = COPY [[t2LDRB_POST1]] 284 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 285 %0:gprnopc = COPY $r0 286 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load 4, align 4) 287 %3:rgpr = t2LDRBi12 %0, 2, 14, $noreg :: (load 4, align 4) 288 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 289 $r0 = COPY %2 290 tBX_RET 14, $noreg, implicit $r0 291 292... 293--- 294name: minsize3 295tracksRegLiveness: true 296registers: 297 - { id: 0, class: gprnopc, preferred-register: '' } 298 - { id: 1, class: rgpr, preferred-register: '' } 299 - { id: 2, class: rgpr, preferred-register: '' } 300 - { id: 3, class: rgpr, preferred-register: '' } 301 - { id: 4, class: rgpr, preferred-register: '' } 302liveins: 303 - { reg: '$r0', virtual-reg: '%0' } 304body: | 305 bb.0: 306 liveins: $r0 307 308 ; CHECK-LABEL: name: minsize3 309 ; CHECK: liveins: $r0 310 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 311 ; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4) 312 ; CHECK: [[t2LDRBi12_1:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 2, 14 /* CC::al */, $noreg :: (load 4) 313 ; CHECK: [[t2LDRBi12_2:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 4, 14 /* CC::al */, $noreg :: (load 4) 314 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 315 ; CHECK: $r0 = COPY [[t2ADDri]] 316 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 317 %0:gprnopc = COPY $r0 318 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load 4, align 4) 319 %3:rgpr = t2LDRBi12 %0, 2, 14, $noreg :: (load 4, align 4) 320 %4:rgpr = t2LDRBi12 %0, 4, 14, $noreg :: (load 4, align 4) 321 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 322 $r0 = COPY %2 323 tBX_RET 14, $noreg, implicit $r0 324 325... 326