1; RUN: llc < %s -mtriple=ve | FileCheck %s
2
3; Function Attrs: nounwind
4define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
5; CHECK-LABEL: br_cc_i1_var:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    xor %s0, %s0, %s1
8; CHECK-NEXT:    brne.w 0, %s0, .LBB{{[0-9]+}}_2
9; CHECK-NEXT:  # %bb.1:
10; CHECK-NEXT:    #APP
11; CHECK-NEXT:    nop
12; CHECK-NEXT:    #NO_APP
13; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
14; CHECK-NEXT:    b.l.t (, %s10)
15  %3 = xor i1 %0, %1
16  br i1 %3, label %5, label %4
17
184:                                                ; preds = %2
19  tail call void asm sideeffect "nop", ""()
20  br label %5
21
225:                                                ; preds = %4, %2
23  ret void
24}
25
26; Function Attrs: nounwind
27define void @br_cc_i8_var(i8 signext %0, i8 signext %1) {
28; CHECK-LABEL: br_cc_i8_var:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    brne.w %s0, %s1, .LBB{{[0-9]+}}_2
31; CHECK-NEXT:  # %bb.1:
32; CHECK-NEXT:    #APP
33; CHECK-NEXT:    nop
34; CHECK-NEXT:    #NO_APP
35; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
36; CHECK-NEXT:    b.l.t (, %s10)
37  %3 = icmp eq i8 %0, %1
38  br i1 %3, label %4, label %5
39
404:                                                ; preds = %2
41  tail call void asm sideeffect "nop", ""()
42  br label %5
43
445:                                                ; preds = %4, %2
45  ret void
46}
47
48; Function Attrs: nounwind
49define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) {
50; CHECK-LABEL: br_cc_u8_var:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    brne.w %s0, %s1, .LBB{{[0-9]+}}_2
53; CHECK-NEXT:  # %bb.1:
54; CHECK-NEXT:    #APP
55; CHECK-NEXT:    nop
56; CHECK-NEXT:    #NO_APP
57; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
58; CHECK-NEXT:    b.l.t (, %s10)
59  %3 = icmp eq i8 %0, %1
60  br i1 %3, label %4, label %5
61
624:                                                ; preds = %2
63  tail call void asm sideeffect "nop", ""()
64  br label %5
65
665:                                                ; preds = %4, %2
67  ret void
68}
69
70; Function Attrs: nounwind
71define void @br_cc_i16_var(i16 signext %0, i16 signext %1) {
72; CHECK-LABEL: br_cc_i16_var:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    brne.w %s0, %s1, .LBB{{[0-9]+}}_2
75; CHECK-NEXT:  # %bb.1:
76; CHECK-NEXT:    #APP
77; CHECK-NEXT:    nop
78; CHECK-NEXT:    #NO_APP
79; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
80; CHECK-NEXT:    b.l.t (, %s10)
81  %3 = icmp eq i16 %0, %1
82  br i1 %3, label %4, label %5
83
844:                                                ; preds = %2
85  tail call void asm sideeffect "nop", ""()
86  br label %5
87
885:                                                ; preds = %4, %2
89  ret void
90}
91
92; Function Attrs: nounwind
93define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) {
94; CHECK-LABEL: br_cc_u16_var:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    brne.w %s0, %s1, .LBB{{[0-9]+}}_2
97; CHECK-NEXT:  # %bb.1:
98; CHECK-NEXT:    #APP
99; CHECK-NEXT:    nop
100; CHECK-NEXT:    #NO_APP
101; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
102; CHECK-NEXT:    b.l.t (, %s10)
103  %3 = icmp eq i16 %0, %1
104  br i1 %3, label %4, label %5
105
1064:                                                ; preds = %2
107  tail call void asm sideeffect "nop", ""()
108  br label %5
109
1105:                                                ; preds = %4, %2
111  ret void
112}
113
114; Function Attrs: nounwind
115define void @br_cc_i32_var(i32 signext %0, i32 signext %1) {
116; CHECK-LABEL: br_cc_i32_var:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    brne.w %s0, %s1, .LBB{{[0-9]+}}_2
119; CHECK-NEXT:  # %bb.1:
120; CHECK-NEXT:    #APP
121; CHECK-NEXT:    nop
122; CHECK-NEXT:    #NO_APP
123; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
124; CHECK-NEXT:    b.l.t (, %s10)
125  %3 = icmp eq i32 %0, %1
126  br i1 %3, label %4, label %5
127
1284:                                                ; preds = %2
129  tail call void asm sideeffect "nop", ""()
130  br label %5
131
1325:                                                ; preds = %4, %2
133  ret void
134}
135
136; Function Attrs: nounwind
137define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) {
138; CHECK-LABEL: br_cc_u32_var:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    brne.w %s0, %s1, .LBB{{[0-9]+}}_2
141; CHECK-NEXT:  # %bb.1:
142; CHECK-NEXT:    #APP
143; CHECK-NEXT:    nop
144; CHECK-NEXT:    #NO_APP
145; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
146; CHECK-NEXT:    b.l.t (, %s10)
147  %3 = icmp eq i32 %0, %1
148  br i1 %3, label %4, label %5
149
1504:                                                ; preds = %2
151  tail call void asm sideeffect "nop", ""()
152  br label %5
153
1545:                                                ; preds = %4, %2
155  ret void
156}
157
158; Function Attrs: nounwind
159define void @br_cc_i64_var(i64 %0, i64 %1) {
160; CHECK-LABEL: br_cc_i64_var:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    brne.l %s0, %s1, .LBB{{[0-9]+}}_2
163; CHECK-NEXT:  # %bb.1:
164; CHECK-NEXT:    #APP
165; CHECK-NEXT:    nop
166; CHECK-NEXT:    #NO_APP
167; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
168; CHECK-NEXT:    b.l.t (, %s10)
169  %3 = icmp eq i64 %0, %1
170  br i1 %3, label %4, label %5
171
1724:                                                ; preds = %2
173  tail call void asm sideeffect "nop", ""()
174  br label %5
175
1765:                                                ; preds = %4, %2
177  ret void
178}
179
180; Function Attrs: nounwind
181define void @br_cc_u64_var(i64 %0, i64 %1) {
182; CHECK-LABEL: br_cc_u64_var:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    brne.l %s0, %s1, .LBB{{[0-9]+}}_2
185; CHECK-NEXT:  # %bb.1:
186; CHECK-NEXT:    #APP
187; CHECK-NEXT:    nop
188; CHECK-NEXT:    #NO_APP
189; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
190; CHECK-NEXT:    b.l.t (, %s10)
191  %3 = icmp eq i64 %0, %1
192  br i1 %3, label %4, label %5
193
1944:                                                ; preds = %2
195  tail call void asm sideeffect "nop", ""()
196  br label %5
197
1985:                                                ; preds = %4, %2
199  ret void
200}
201
202; Function Attrs: nounwind
203define void @br_cc_i128_var(i128 %0, i128 %1) {
204; CHECK-LABEL: br_cc_i128_var:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    xor %s1, %s1, %s3
207; CHECK-NEXT:    xor %s0, %s0, %s2
208; CHECK-NEXT:    or %s0, %s0, %s1
209; CHECK-NEXT:    brne.l 0, %s0, .LBB{{[0-9]+}}_2
210; CHECK-NEXT:  # %bb.1:
211; CHECK-NEXT:    #APP
212; CHECK-NEXT:    nop
213; CHECK-NEXT:    #NO_APP
214; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
215; CHECK-NEXT:    b.l.t (, %s10)
216  %3 = icmp eq i128 %0, %1
217  br i1 %3, label %4, label %5
218
2194:                                                ; preds = %2
220  tail call void asm sideeffect "nop", ""()
221  br label %5
222
2235:                                                ; preds = %4, %2
224  ret void
225}
226
227; Function Attrs: nounwind
228define void @br_cc_u128_var(i128 %0, i128 %1) {
229; CHECK-LABEL: br_cc_u128_var:
230; CHECK:       # %bb.0:
231; CHECK-NEXT:    xor %s1, %s1, %s3
232; CHECK-NEXT:    xor %s0, %s0, %s2
233; CHECK-NEXT:    or %s0, %s0, %s1
234; CHECK-NEXT:    brne.l 0, %s0, .LBB{{[0-9]+}}_2
235; CHECK-NEXT:  # %bb.1:
236; CHECK-NEXT:    #APP
237; CHECK-NEXT:    nop
238; CHECK-NEXT:    #NO_APP
239; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
240; CHECK-NEXT:    b.l.t (, %s10)
241  %3 = icmp eq i128 %0, %1
242  br i1 %3, label %4, label %5
243
2444:                                                ; preds = %2
245  tail call void asm sideeffect "nop", ""()
246  br label %5
247
2485:                                                ; preds = %4, %2
249  ret void
250}
251
252; Function Attrs: nounwind
253define void @br_cc_float_var(float %0, float %1) {
254; CHECK-LABEL: br_cc_float_var:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    brne.s %s0, %s1, .LBB{{[0-9]+}}_2
257; CHECK-NEXT:  # %bb.1:
258; CHECK-NEXT:    #APP
259; CHECK-NEXT:    nop
260; CHECK-NEXT:    #NO_APP
261; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
262; CHECK-NEXT:    b.l.t (, %s10)
263  %3 = fcmp fast oeq float %0, %1
264  br i1 %3, label %4, label %5
265
2664:                                                ; preds = %2
267  tail call void asm sideeffect "nop", ""()
268  br label %5
269
2705:                                                ; preds = %4, %2
271  ret void
272}
273
274; Function Attrs: nounwind
275define void @br_cc_double_var(double %0, double %1) {
276; CHECK-LABEL: br_cc_double_var:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    brne.d %s0, %s1, .LBB{{[0-9]+}}_2
279; CHECK-NEXT:  # %bb.1:
280; CHECK-NEXT:    #APP
281; CHECK-NEXT:    nop
282; CHECK-NEXT:    #NO_APP
283; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
284; CHECK-NEXT:    b.l.t (, %s10)
285  %3 = fcmp fast oeq double %0, %1
286  br i1 %3, label %4, label %5
287
2884:                                                ; preds = %2
289  tail call void asm sideeffect "nop", ""()
290  br label %5
291
2925:                                                ; preds = %4, %2
293  ret void
294}
295
296; Function Attrs: nounwind
297define void @br_cc_quad_var(fp128 %0, fp128 %1) {
298; CHECK-LABEL: br_cc_quad_var:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    fcmp.q %s0, %s2, %s0
301; CHECK-NEXT:    brne.d 0, %s0, .LBB{{[0-9]+}}_2
302; CHECK-NEXT:  # %bb.1:
303; CHECK-NEXT:    #APP
304; CHECK-NEXT:    nop
305; CHECK-NEXT:    #NO_APP
306; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
307; CHECK-NEXT:    b.l.t (, %s10)
308  %3 = fcmp fast oeq fp128 %0, %1
309  br i1 %3, label %4, label %5
310
3114:                                                ; preds = %2
312  tail call void asm sideeffect "nop", ""()
313  br label %5
314
3155:                                                ; preds = %4, %2
316  ret void
317}
318
319; Function Attrs: nounwind
320define void @br_cc_i1_imm(i1 zeroext %0) {
321; CHECK-LABEL: br_cc_i1_imm:
322; CHECK:       # %bb.0:
323; CHECK-NEXT:    brne.w 0, %s0, .LBB{{[0-9]+}}_2
324; CHECK-NEXT:  # %bb.1:
325; CHECK-NEXT:    #APP
326; CHECK-NEXT:    nop
327; CHECK-NEXT:    #NO_APP
328; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
329; CHECK-NEXT:    b.l.t (, %s10)
330  br i1 %0, label %3, label %2
331
3322:                                                ; preds = %1
333  tail call void asm sideeffect "nop", ""()
334  br label %3
335
3363:                                                ; preds = %2, %1
337  ret void
338}
339
340; Function Attrs: nounwind
341define void @br_cc_i8_imm(i8 signext %0) {
342; CHECK-LABEL: br_cc_i8_imm:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    brlt.w -10, %s0, .LBB{{[0-9]+}}_2
345; CHECK-NEXT:  # %bb.1:
346; CHECK-NEXT:    #APP
347; CHECK-NEXT:    nop
348; CHECK-NEXT:    #NO_APP
349; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
350; CHECK-NEXT:    b.l.t (, %s10)
351  %2 = icmp slt i8 %0, -9
352  br i1 %2, label %3, label %4
353
3543:                                                ; preds = %1
355  tail call void asm sideeffect "nop", ""()
356  br label %4
357
3584:                                                ; preds = %3, %1
359  ret void
360}
361
362; Function Attrs: nounwind
363define void @br_cc_u8_imm(i8 zeroext %0) {
364; CHECK-LABEL: br_cc_u8_imm:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    cmpu.w %s0, 8, %s0
367; CHECK-NEXT:    brgt.w 0, %s0, .LBB{{[0-9]+}}_2
368; CHECK-NEXT:  # %bb.1:
369; CHECK-NEXT:    #APP
370; CHECK-NEXT:    nop
371; CHECK-NEXT:    #NO_APP
372; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
373; CHECK-NEXT:    b.l.t (, %s10)
374  %2 = icmp ult i8 %0, 9
375  br i1 %2, label %3, label %4
376
3773:                                                ; preds = %1
378  tail call void asm sideeffect "nop", ""()
379  br label %4
380
3814:                                                ; preds = %3, %1
382  ret void
383}
384
385; Function Attrs: nounwind
386define void @br_cc_i16_imm(i16 signext %0) {
387; CHECK-LABEL: br_cc_i16_imm:
388; CHECK:       # %bb.0:
389; CHECK-NEXT:    brlt.w 62, %s0, .LBB{{[0-9]+}}_2
390; CHECK-NEXT:  # %bb.1:
391; CHECK-NEXT:    #APP
392; CHECK-NEXT:    nop
393; CHECK-NEXT:    #NO_APP
394; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
395; CHECK-NEXT:    b.l.t (, %s10)
396  %2 = icmp slt i16 %0, 63
397  br i1 %2, label %3, label %4
398
3993:                                                ; preds = %1
400  tail call void asm sideeffect "nop", ""()
401  br label %4
402
4034:                                                ; preds = %3, %1
404  ret void
405}
406
407; Function Attrs: nounwind
408define void @br_cc_u16_imm(i16 zeroext %0) {
409; CHECK-LABEL: br_cc_u16_imm:
410; CHECK:       # %bb.0:
411; CHECK-NEXT:    cmpu.w %s0, 63, %s0
412; CHECK-NEXT:    brgt.w 0, %s0, .LBB{{[0-9]+}}_2
413; CHECK-NEXT:  # %bb.1:
414; CHECK-NEXT:    #APP
415; CHECK-NEXT:    nop
416; CHECK-NEXT:    #NO_APP
417; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
418; CHECK-NEXT:    b.l.t (, %s10)
419  %2 = icmp ult i16 %0, 64
420  br i1 %2, label %3, label %4
421
4223:                                                ; preds = %1
423  tail call void asm sideeffect "nop", ""()
424  br label %4
425
4264:                                                ; preds = %3, %1
427  ret void
428}
429
430; Function Attrs: nounwind
431define void @br_cc_i32_imm(i32 signext %0) {
432; CHECK-LABEL: br_cc_i32_imm:
433; CHECK:       # %bb.0:
434; CHECK-NEXT:    brlt.w 63, %s0, .LBB{{[0-9]+}}_2
435; CHECK-NEXT:  # %bb.1:
436; CHECK-NEXT:    #APP
437; CHECK-NEXT:    nop
438; CHECK-NEXT:    #NO_APP
439; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
440; CHECK-NEXT:    b.l.t (, %s10)
441  %2 = icmp slt i32 %0, 64
442  br i1 %2, label %3, label %4
443
4443:                                                ; preds = %1
445  tail call void asm sideeffect "nop", ""()
446  br label %4
447
4484:                                                ; preds = %3, %1
449  ret void
450}
451
452; Function Attrs: nounwind
453define void @br_cc_u32_imm(i32 zeroext %0) {
454; CHECK-LABEL: br_cc_u32_imm:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    cmpu.w %s0, 63, %s0
457; CHECK-NEXT:    brgt.w 0, %s0, .LBB{{[0-9]+}}_2
458; CHECK-NEXT:  # %bb.1:
459; CHECK-NEXT:    #APP
460; CHECK-NEXT:    nop
461; CHECK-NEXT:    #NO_APP
462; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
463; CHECK-NEXT:    b.l.t (, %s10)
464  %2 = icmp ult i32 %0, 64
465  br i1 %2, label %3, label %4
466
4673:                                                ; preds = %1
468  tail call void asm sideeffect "nop", ""()
469  br label %4
470
4714:                                                ; preds = %3, %1
472  ret void
473}
474
475; Function Attrs: nounwind
476define void @br_cc_i64_imm(i64 %0) {
477; CHECK-LABEL: br_cc_i64_imm:
478; CHECK:       # %bb.0:
479; CHECK-NEXT:    brlt.l 63, %s0, .LBB{{[0-9]+}}_2
480; CHECK-NEXT:  # %bb.1:
481; CHECK-NEXT:    #APP
482; CHECK-NEXT:    nop
483; CHECK-NEXT:    #NO_APP
484; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
485; CHECK-NEXT:    b.l.t (, %s10)
486  %2 = icmp slt i64 %0, 64
487  br i1 %2, label %3, label %4
488
4893:                                                ; preds = %1
490  tail call void asm sideeffect "nop", ""()
491  br label %4
492
4934:                                                ; preds = %3, %1
494  ret void
495}
496
497; Function Attrs: nounwind
498define void @br_cc_u64_imm(i64 %0) {
499; CHECK-LABEL: br_cc_u64_imm:
500; CHECK:       # %bb.0:
501; CHECK-NEXT:    cmpu.l %s0, 63, %s0
502; CHECK-NEXT:    brgt.l 0, %s0, .LBB{{[0-9]+}}_2
503; CHECK-NEXT:  # %bb.1:
504; CHECK-NEXT:    #APP
505; CHECK-NEXT:    nop
506; CHECK-NEXT:    #NO_APP
507; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
508; CHECK-NEXT:    b.l.t (, %s10)
509  %2 = icmp ult i64 %0, 64
510  br i1 %2, label %3, label %4
511
5123:                                                ; preds = %1
513  tail call void asm sideeffect "nop", ""()
514  br label %4
515
5164:                                                ; preds = %3, %1
517  ret void
518}
519
520; Function Attrs: nounwind
521define void @br_cc_i128_imm(i128 %0) {
522; CHECK-LABEL: br_cc_i128_imm:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    or %s2, 0, (0)1
525; CHECK-NEXT:    cmps.l %s1, %s1, (0)1
526; CHECK-NEXT:    or %s3, 0, (0)1
527; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
528; CHECK-NEXT:    cmpu.l %s0, %s0, (58)0
529; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
530; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
531; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
532; CHECK-NEXT:  # %bb.1:
533; CHECK-NEXT:    #APP
534; CHECK-NEXT:    nop
535; CHECK-NEXT:    #NO_APP
536; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
537; CHECK-NEXT:    b.l.t (, %s10)
538  %2 = icmp slt i128 %0, 64
539  br i1 %2, label %3, label %4
540
5413:                                                ; preds = %1
542  tail call void asm sideeffect "nop", ""()
543  br label %4
544
5454:                                                ; preds = %3, %1
546  ret void
547}
548
549; Function Attrs: nounwind
550define void @br_cc_u128_imm(i128 %0) {
551; CHECK-LABEL: br_cc_u128_imm:
552; CHECK:       # %bb.0:
553; CHECK-NEXT:    or %s2, 0, (0)1
554; CHECK-NEXT:    cmps.l %s1, %s1, (0)1
555; CHECK-NEXT:    or %s3, 0, (0)1
556; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
557; CHECK-NEXT:    cmpu.l %s0, %s0, (58)0
558; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
559; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
560; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
561; CHECK-NEXT:  # %bb.1:
562; CHECK-NEXT:    #APP
563; CHECK-NEXT:    nop
564; CHECK-NEXT:    #NO_APP
565; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
566; CHECK-NEXT:    b.l.t (, %s10)
567  %2 = icmp ult i128 %0, 64
568  br i1 %2, label %3, label %4
569
5703:                                                ; preds = %1
571  tail call void asm sideeffect "nop", ""()
572  br label %4
573
5744:                                                ; preds = %3, %1
575  ret void
576}
577
578; Function Attrs: nounwind
579define void @br_cc_float_imm(float %0) {
580; CHECK-LABEL: br_cc_float_imm:
581; CHECK:       # %bb.0:
582; CHECK-NEXT:    brle.s 0, %s0, .LBB{{[0-9]+}}_2
583; CHECK-NEXT:  # %bb.1:
584; CHECK-NEXT:    #APP
585; CHECK-NEXT:    nop
586; CHECK-NEXT:    #NO_APP
587; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
588; CHECK-NEXT:    b.l.t (, %s10)
589  %2 = fcmp fast olt float %0, 0.000000e+00
590  br i1 %2, label %3, label %4
591
5923:                                                ; preds = %1
593  tail call void asm sideeffect "nop", ""()
594  br label %4
595
5964:                                                ; preds = %3, %1
597  ret void
598}
599
600; Function Attrs: nounwind
601define void @br_cc_double_imm(double %0) {
602; CHECK-LABEL: br_cc_double_imm:
603; CHECK:       # %bb.0:
604; CHECK-NEXT:    brle.d 0, %s0, .LBB{{[0-9]+}}_2
605; CHECK-NEXT:  # %bb.1:
606; CHECK-NEXT:    #APP
607; CHECK-NEXT:    nop
608; CHECK-NEXT:    #NO_APP
609; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
610; CHECK-NEXT:    b.l.t (, %s10)
611  %2 = fcmp fast olt double %0, 0.000000e+00
612  br i1 %2, label %3, label %4
613
6143:                                                ; preds = %1
615  tail call void asm sideeffect "nop", ""()
616  br label %4
617
6184:                                                ; preds = %3, %1
619  ret void
620}
621
622; Function Attrs: nounwind
623define void @br_cc_quad_imm(fp128 %0) {
624; CHECK-LABEL: br_cc_quad_imm:
625; CHECK:       # %bb.0:
626; CHECK-NEXT:    lea %s2, .LCPI{{[0-9]+}}_0@lo
627; CHECK-NEXT:    and %s2, %s2, (32)0
628; CHECK-NEXT:    lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
629; CHECK-NEXT:    ld %s4, 8(, %s2)
630; CHECK-NEXT:    ld %s5, (, %s2)
631; CHECK-NEXT:    fcmp.q %s0, %s4, %s0
632; CHECK-NEXT:    brge.d 0, %s0, .LBB{{[0-9]+}}_2
633; CHECK-NEXT:  # %bb.1:
634; CHECK-NEXT:    #APP
635; CHECK-NEXT:    nop
636; CHECK-NEXT:    #NO_APP
637; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
638; CHECK-NEXT:    b.l.t (, %s10)
639  %2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000
640  br i1 %2, label %3, label %4
641
6423:                                                ; preds = %1
643  tail call void asm sideeffect "nop", ""()
644  br label %4
645
6464:                                                ; preds = %3, %1
647  ret void
648}
649
650; Function Attrs: nounwind
651define void @br_cc_imm_i1(i1 zeroext %0) {
652; CHECK-LABEL: br_cc_imm_i1:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    breq.w 0, %s0, .LBB{{[0-9]+}}_2
655; CHECK-NEXT:  # %bb.1:
656; CHECK-NEXT:    #APP
657; CHECK-NEXT:    nop
658; CHECK-NEXT:    #NO_APP
659; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
660; CHECK-NEXT:    b.l.t (, %s10)
661  br i1 %0, label %2, label %3
662
6632:                                                ; preds = %1
664  tail call void asm sideeffect "nop", ""()
665  br label %3
666
6673:                                                ; preds = %2, %1
668  ret void
669}
670
671; Function Attrs: nounwind
672define void @br_cc_imm_i8(i8 signext %0) {
673; CHECK-LABEL: br_cc_imm_i8:
674; CHECK:       # %bb.0:
675; CHECK-NEXT:    brgt.w -9, %s0, .LBB{{[0-9]+}}_2
676; CHECK-NEXT:  # %bb.1:
677; CHECK-NEXT:    #APP
678; CHECK-NEXT:    nop
679; CHECK-NEXT:    #NO_APP
680; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
681; CHECK-NEXT:    b.l.t (, %s10)
682  %2 = icmp sgt i8 %0, -10
683  br i1 %2, label %3, label %4
684
6853:                                                ; preds = %1
686  tail call void asm sideeffect "nop", ""()
687  br label %4
688
6894:                                                ; preds = %3, %1
690  ret void
691}
692
693; Function Attrs: nounwind
694define void @br_cc_imm_u8(i8 zeroext %0) {
695; CHECK-LABEL: br_cc_imm_u8:
696; CHECK:       # %bb.0:
697; CHECK-NEXT:    cmpu.w %s0, 9, %s0
698; CHECK-NEXT:    brlt.w 0, %s0, .LBB{{[0-9]+}}_2
699; CHECK-NEXT:  # %bb.1:
700; CHECK-NEXT:    #APP
701; CHECK-NEXT:    nop
702; CHECK-NEXT:    #NO_APP
703; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
704; CHECK-NEXT:    b.l.t (, %s10)
705  %2 = icmp ugt i8 %0, 8
706  br i1 %2, label %3, label %4
707
7083:                                                ; preds = %1
709  tail call void asm sideeffect "nop", ""()
710  br label %4
711
7124:                                                ; preds = %3, %1
713  ret void
714}
715
716; Function Attrs: nounwind
717define void @br_cc_imm_i16(i16 signext %0) {
718; CHECK-LABEL: br_cc_imm_i16:
719; CHECK:       # %bb.0:
720; CHECK-NEXT:    brgt.w 63, %s0, .LBB{{[0-9]+}}_2
721; CHECK-NEXT:  # %bb.1:
722; CHECK-NEXT:    #APP
723; CHECK-NEXT:    nop
724; CHECK-NEXT:    #NO_APP
725; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
726; CHECK-NEXT:    b.l.t (, %s10)
727  %2 = icmp sgt i16 %0, 62
728  br i1 %2, label %3, label %4
729
7303:                                                ; preds = %1
731  tail call void asm sideeffect "nop", ""()
732  br label %4
733
7344:                                                ; preds = %3, %1
735  ret void
736}
737
738; Function Attrs: nounwind
739define void @br_cc_imm_u16(i16 zeroext %0) {
740; CHECK-LABEL: br_cc_imm_u16:
741; CHECK:       # %bb.0:
742; CHECK-NEXT:    lea %s1, 64
743; CHECK-NEXT:    cmpu.w %s0, %s1, %s0
744; CHECK-NEXT:    brlt.w 0, %s0, .LBB{{[0-9]+}}_2
745; CHECK-NEXT:  # %bb.1:
746; CHECK-NEXT:    #APP
747; CHECK-NEXT:    nop
748; CHECK-NEXT:    #NO_APP
749; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
750; CHECK-NEXT:    b.l.t (, %s10)
751  %2 = icmp ugt i16 %0, 63
752  br i1 %2, label %3, label %4
753
7543:                                                ; preds = %1
755  tail call void asm sideeffect "nop", ""()
756  br label %4
757
7584:                                                ; preds = %3, %1
759  ret void
760}
761
762; Function Attrs: nounwind
763define void @br_cc_imm_i32(i32 signext %0) {
764; CHECK-LABEL: br_cc_imm_i32:
765; CHECK:       # %bb.0:
766; CHECK-NEXT:    brgt.w -64, %s0, .LBB{{[0-9]+}}_2
767; CHECK-NEXT:  # %bb.1:
768; CHECK-NEXT:    #APP
769; CHECK-NEXT:    nop
770; CHECK-NEXT:    #NO_APP
771; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
772; CHECK-NEXT:    b.l.t (, %s10)
773  %2 = icmp sgt i32 %0, -65
774  br i1 %2, label %3, label %4
775
7763:                                                ; preds = %1
777  tail call void asm sideeffect "nop", ""()
778  br label %4
779
7804:                                                ; preds = %3, %1
781  ret void
782}
783
784; Function Attrs: nounwind
785define void @br_cc_imm_u32(i32 zeroext %0) {
786; CHECK-LABEL: br_cc_imm_u32:
787; CHECK:       # %bb.0:
788; CHECK-NEXT:    cmpu.w %s0, -64, %s0
789; CHECK-NEXT:    brlt.w 0, %s0, .LBB{{[0-9]+}}_2
790; CHECK-NEXT:  # %bb.1:
791; CHECK-NEXT:    #APP
792; CHECK-NEXT:    nop
793; CHECK-NEXT:    #NO_APP
794; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
795; CHECK-NEXT:    b.l.t (, %s10)
796  %2 = icmp ugt i32 %0, -65
797  br i1 %2, label %3, label %4
798
7993:                                                ; preds = %1
800  tail call void asm sideeffect "nop", ""()
801  br label %4
802
8034:                                                ; preds = %3, %1
804  ret void
805}
806
807; Function Attrs: nounwind
808define void @br_cc_imm_i64(i64 %0) {
809; CHECK-LABEL: br_cc_imm_i64:
810; CHECK:       # %bb.0:
811; CHECK-NEXT:    brgt.l -64, %s0, .LBB{{[0-9]+}}_2
812; CHECK-NEXT:  # %bb.1:
813; CHECK-NEXT:    #APP
814; CHECK-NEXT:    nop
815; CHECK-NEXT:    #NO_APP
816; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
817; CHECK-NEXT:    b.l.t (, %s10)
818  %2 = icmp sgt i64 %0, -65
819  br i1 %2, label %3, label %4
820
8213:                                                ; preds = %1
822  tail call void asm sideeffect "nop", ""()
823  br label %4
824
8254:                                                ; preds = %3, %1
826  ret void
827}
828
829; Function Attrs: nounwind
830define void @br_cc_imm_u64(i64 %0) {
831; CHECK-LABEL: br_cc_imm_u64:
832; CHECK:       # %bb.0:
833; CHECK-NEXT:    cmpu.l %s0, -64, %s0
834; CHECK-NEXT:    brlt.l 0, %s0, .LBB{{[0-9]+}}_2
835; CHECK-NEXT:  # %bb.1:
836; CHECK-NEXT:    #APP
837; CHECK-NEXT:    nop
838; CHECK-NEXT:    #NO_APP
839; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
840; CHECK-NEXT:    b.l.t (, %s10)
841  %2 = icmp ugt i64 %0, -65
842  br i1 %2, label %3, label %4
843
8443:                                                ; preds = %1
845  tail call void asm sideeffect "nop", ""()
846  br label %4
847
8484:                                                ; preds = %3, %1
849  ret void
850}
851
852; Function Attrs: nounwind
853define void @br_cc_imm_i128(i128 %0) {
854; CHECK-LABEL: br_cc_imm_i128:
855; CHECK:       # %bb.0:
856; CHECK-NEXT:    cmps.l %s1, %s1, (0)0
857; CHECK-NEXT:    or %s2, 0, (0)1
858; CHECK-NEXT:    or %s3, 0, (0)1
859; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s1
860; CHECK-NEXT:    cmpu.l %s0, %s0, (58)1
861; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
862; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
863; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
864; CHECK-NEXT:  # %bb.1:
865; CHECK-NEXT:    #APP
866; CHECK-NEXT:    nop
867; CHECK-NEXT:    #NO_APP
868; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
869; CHECK-NEXT:    b.l.t (, %s10)
870  %2 = icmp sgt i128 %0, -65
871  br i1 %2, label %3, label %4
872
8733:                                                ; preds = %1
874  tail call void asm sideeffect "nop", ""()
875  br label %4
876
8774:                                                ; preds = %3, %1
878  ret void
879}
880
881; Function Attrs: nounwind
882define void @br_cc_imm_u128(i128 %0) {
883; CHECK-LABEL: br_cc_imm_u128:
884; CHECK:       # %bb.0:
885; CHECK-NEXT:    cmps.l %s1, %s1, (0)0
886; CHECK-NEXT:    or %s2, 0, (0)1
887; CHECK-NEXT:    or %s3, 0, (0)1
888; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
889; CHECK-NEXT:    cmpu.l %s0, %s0, (58)1
890; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
891; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
892; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
893; CHECK-NEXT:  # %bb.1:
894; CHECK-NEXT:    #APP
895; CHECK-NEXT:    nop
896; CHECK-NEXT:    #NO_APP
897; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
898; CHECK-NEXT:    b.l.t (, %s10)
899  %2 = icmp ugt i128 %0, -65
900  br i1 %2, label %3, label %4
901
9023:                                                ; preds = %1
903  tail call void asm sideeffect "nop", ""()
904  br label %4
905
9064:                                                ; preds = %3, %1
907  ret void
908}
909
910; Function Attrs: nounwind
911define void @br_cc_imm_float(float %0) {
912; CHECK-LABEL: br_cc_imm_float:
913; CHECK:       # %bb.0:
914; CHECK-NEXT:    brgt.s 0, %s0, .LBB{{[0-9]+}}_2
915; CHECK-NEXT:  # %bb.1:
916; CHECK-NEXT:    #APP
917; CHECK-NEXT:    nop
918; CHECK-NEXT:    #NO_APP
919; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
920; CHECK-NEXT:    b.l.t (, %s10)
921  %2 = fcmp fast ult float %0, 0.000000e+00
922  br i1 %2, label %4, label %3
923
9243:                                                ; preds = %1
925  tail call void asm sideeffect "nop", ""()
926  br label %4
927
9284:                                                ; preds = %3, %1
929  ret void
930}
931
932; Function Attrs: nounwind
933define void @br_cc_imm_double(double %0) {
934; CHECK-LABEL: br_cc_imm_double:
935; CHECK:       # %bb.0:
936; CHECK-NEXT:    brgt.d 0, %s0, .LBB{{[0-9]+}}_2
937; CHECK-NEXT:  # %bb.1:
938; CHECK-NEXT:    #APP
939; CHECK-NEXT:    nop
940; CHECK-NEXT:    #NO_APP
941; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
942; CHECK-NEXT:    b.l.t (, %s10)
943  %2 = fcmp fast ult double %0, 0.000000e+00
944  br i1 %2, label %4, label %3
945
9463:                                                ; preds = %1
947  tail call void asm sideeffect "nop", ""()
948  br label %4
949
9504:                                                ; preds = %3, %1
951  ret void
952}
953
954; Function Attrs: nounwind
955define void @br_cc_imm_quad(fp128 %0) {
956; CHECK-LABEL: br_cc_imm_quad:
957; CHECK:       # %bb.0:
958; CHECK-NEXT:    lea %s2, .LCPI{{[0-9]+}}_0@lo
959; CHECK-NEXT:    and %s2, %s2, (32)0
960; CHECK-NEXT:    lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
961; CHECK-NEXT:    ld %s4, 8(, %s2)
962; CHECK-NEXT:    ld %s5, (, %s2)
963; CHECK-NEXT:    fcmp.q %s0, %s4, %s0
964; CHECK-NEXT:    brlt.d 0, %s0, .LBB{{[0-9]+}}_2
965; CHECK-NEXT:  # %bb.1:
966; CHECK-NEXT:    #APP
967; CHECK-NEXT:    nop
968; CHECK-NEXT:    #NO_APP
969; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
970; CHECK-NEXT:    b.l.t (, %s10)
971  %2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000
972  br i1 %2, label %4, label %3
973
9743:                                                ; preds = %1
975  tail call void asm sideeffect "nop", ""()
976  br label %4
977
9784:                                                ; preds = %3, %1
979  ret void
980}
981