1; RUN: llc < %s -mtriple=ve | FileCheck %s
2; RUN: llc < %s -mtriple=ve -relocation-model=pic \
3; RUN:     | FileCheck %s -check-prefix=PIC
4
5@switch.table.br_jt4 = private unnamed_addr constant [4 x i32] [i32 3, i32 0, i32 4, i32 7], align 4
6@switch.table.br_jt7 = private unnamed_addr constant [9 x i32] [i32 3, i32 0, i32 4, i32 7, i32 3, i32 3, i32 5, i32 11, i32 10], align 4
7@switch.table.br_jt8 = private unnamed_addr constant [9 x i32] [i32 3, i32 0, i32 4, i32 7, i32 3, i32 1, i32 5, i32 11, i32 10], align 4
8
9; Function Attrs: norecurse nounwind readnone
10define signext i32 @br_jt3(i32 signext %0) {
11; CHECK-LABEL: br_jt3:
12; CHECK:       # %bb.0:
13; CHECK-NEXT:    and %s0, %s0, (32)0
14; CHECK-NEXT:    breq.w 1, %s0, .LBB{{[0-9]+}}_1
15; CHECK-NEXT:  # %bb.2:
16; CHECK-NEXT:    breq.w 4, %s0, .LBB{{[0-9]+}}_5
17; CHECK-NEXT:  # %bb.3:
18; CHECK-NEXT:    brne.w 2, %s0, .LBB{{[0-9]+}}_6
19; CHECK-NEXT:  # %bb.4:
20; CHECK-NEXT:    or %s0, 0, (0)1
21; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
22; CHECK-NEXT:    b.l.t (, %s10)
23; CHECK-NEXT:  .LBB{{[0-9]+}}_1:
24; CHECK-NEXT:    or %s0, 3, (0)1
25; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
26; CHECK-NEXT:    b.l.t (, %s10)
27; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
28; CHECK-NEXT:    or %s0, 7, (0)1
29; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
30; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
31; CHECK-NEXT:    b.l.t (, %s10)
32;
33; PIC-LABEL: br_jt3:
34; PIC:       # %bb.0:
35; PIC-NEXT:    and %s0, %s0, (32)0
36; PIC-NEXT:    breq.w 1, %s0, .LBB0_1
37; PIC-NEXT:  # %bb.2:
38; PIC-NEXT:    breq.w 4, %s0, .LBB0_5
39; PIC-NEXT:  # %bb.3:
40; PIC-NEXT:    brne.w 2, %s0, .LBB0_6
41; PIC-NEXT:  # %bb.4:
42; PIC-NEXT:    or %s0, 0, (0)1
43; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
44; PIC-NEXT:    b.l.t (, %s10)
45; PIC-NEXT:  .LBB0_1:
46; PIC-NEXT:    or %s0, 3, (0)1
47; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
48; PIC-NEXT:    b.l.t (, %s10)
49; PIC-NEXT:  .LBB0_5:
50; PIC-NEXT:    or %s0, 7, (0)1
51; PIC-NEXT:  .LBB0_6:
52; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
53; PIC-NEXT:    b.l.t (, %s10)
54  switch i32 %0, label %4 [
55    i32 1, label %5
56    i32 2, label %2
57    i32 4, label %3
58  ]
59
602:                                                ; preds = %1
61  br label %5
62
633:                                                ; preds = %1
64  br label %5
65
664:                                                ; preds = %1
67  br label %5
68
695:                                                ; preds = %1, %4, %3, %2
70  %6 = phi i32 [ %0, %4 ], [ 7, %3 ], [ 0, %2 ], [ 3, %1 ]
71  ret i32 %6
72}
73
74; Function Attrs: norecurse nounwind readnone
75define signext i32 @br_jt4(i32 signext %0) {
76; CHECK-LABEL: br_jt4:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    and %s0, %s0, (32)0
79; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
80; CHECK-NEXT:    cmpu.w %s2, 3, %s1
81; CHECK-NEXT:    brgt.w 0, %s2, .LBB{{[0-9]+}}_2
82; CHECK-NEXT:  # %bb.1:
83; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
84; CHECK-NEXT:    sll %s0, %s0, 2
85; CHECK-NEXT:    lea %s1, .Lswitch.table.br_jt4@lo
86; CHECK-NEXT:    and %s1, %s1, (32)0
87; CHECK-NEXT:    lea.sl %s1, .Lswitch.table.br_jt4@hi(, %s1)
88; CHECK-NEXT:    ldl.sx %s0, (%s0, %s1)
89; CHECK-NEXT:    b.l.t (, %s10)
90; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
91; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
92; CHECK-NEXT:    b.l.t (, %s10)
93;
94; PIC-LABEL: br_jt4:
95; PIC:       # %bb.0:
96; PIC-NEXT:    st %s15, 24(, %s11)
97; PIC-NEXT:    st %s16, 32(, %s11)
98; PIC-NEXT:    and %s0, %s0, (32)0
99; PIC-NEXT:    adds.w.sx %s1, -1, %s0
100; PIC-NEXT:    cmpu.w %s2, 3, %s1
101; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
102; PIC-NEXT:    and %s15, %s15, (32)0
103; PIC-NEXT:    sic %s16
104; PIC-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
105; PIC-NEXT:    brgt.w 0, %s2, .LBB1_2
106; PIC-NEXT:  # %bb.1:
107; PIC-NEXT:    adds.w.sx %s0, %s1, (0)1
108; PIC-NEXT:    sll %s0, %s0, 2
109; PIC-NEXT:    lea %s1, .Lswitch.table.br_jt4@gotoff_lo
110; PIC-NEXT:    and %s1, %s1, (32)0
111; PIC-NEXT:    lea.sl %s1, .Lswitch.table.br_jt4@gotoff_hi(%s1, %s15)
112; PIC-NEXT:    ldl.sx %s0, (%s0, %s1)
113; PIC-NEXT:    br.l.t .LBB1_3
114; PIC-NEXT:  .LBB1_2:
115; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
116; PIC-NEXT:  .LBB1_3:
117; PIC-NEXT:    ld %s16, 32(, %s11)
118; PIC-NEXT:    ld %s15, 24(, %s11)
119; PIC-NEXT:    b.l.t (, %s10)
120  %2 = add i32 %0, -1
121  %3 = icmp ult i32 %2, 4
122  br i1 %3, label %4, label %8
123
1244:                                                ; preds = %1
125  %5 = sext i32 %2 to i64
126  %6 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.br_jt4, i64 0, i64 %5
127  %7 = load i32, i32* %6, align 4
128  ret i32 %7
129
1308:                                                ; preds = %1
131  ret i32 %0
132}
133
134; Function Attrs: norecurse nounwind readnone
135define signext i32 @br_jt7(i32 signext %0) {
136; CHECK-LABEL: br_jt7:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    and %s0, %s0, (32)0
139; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
140; CHECK-NEXT:    cmpu.w %s2, 8, %s1
141; CHECK-NEXT:    brgt.w 0, %s2, .LBB{{[0-9]+}}_3
142; CHECK-NEXT:  # %bb.1:
143; CHECK-NEXT:    and %s2, %s1, (48)0
144; CHECK-NEXT:    lea %s3, 463
145; CHECK-NEXT:    and %s3, %s3, (32)0
146; CHECK-NEXT:    srl %s2, %s3, %s2
147; CHECK-NEXT:    and %s2, 1, %s2
148; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
149; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
150; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
151; CHECK-NEXT:    b.l.t (, %s10)
152; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
153; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
154; CHECK-NEXT:    sll %s0, %s0, 2
155; CHECK-NEXT:    lea %s1, .Lswitch.table.br_jt7@lo
156; CHECK-NEXT:    and %s1, %s1, (32)0
157; CHECK-NEXT:    lea.sl %s1, .Lswitch.table.br_jt7@hi(, %s1)
158; CHECK-NEXT:    ldl.sx %s0, (%s0, %s1)
159; CHECK-NEXT:    b.l.t (, %s10)
160;
161; PIC-LABEL: br_jt7:
162; PIC:       # %bb.0:
163; PIC-NEXT:    st %s15, 24(, %s11)
164; PIC-NEXT:    st %s16, 32(, %s11)
165; PIC-NEXT:    and %s0, %s0, (32)0
166; PIC-NEXT:    adds.w.sx %s1, -1, %s0
167; PIC-NEXT:    cmpu.w %s2, 8, %s1
168; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
169; PIC-NEXT:    and %s15, %s15, (32)0
170; PIC-NEXT:    sic %s16
171; PIC-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
172; PIC-NEXT:    brgt.w 0, %s2, .LBB2_3
173; PIC-NEXT:  # %bb.1:
174; PIC-NEXT:    and %s2, %s1, (48)0
175; PIC-NEXT:    lea %s3, 463
176; PIC-NEXT:    and %s3, %s3, (32)0
177; PIC-NEXT:    srl %s2, %s3, %s2
178; PIC-NEXT:    and %s2, 1, %s2
179; PIC-NEXT:    brne.w 0, %s2, .LBB2_2
180; PIC-NEXT:  .LBB2_3:
181; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
182; PIC-NEXT:    br.l.t .LBB2_4
183; PIC-NEXT:  .LBB2_2:
184; PIC-NEXT:    adds.w.sx %s0, %s1, (0)1
185; PIC-NEXT:    sll %s0, %s0, 2
186; PIC-NEXT:    lea %s1, .Lswitch.table.br_jt7@gotoff_lo
187; PIC-NEXT:    and %s1, %s1, (32)0
188; PIC-NEXT:    lea.sl %s1, .Lswitch.table.br_jt7@gotoff_hi(%s1, %s15)
189; PIC-NEXT:    ldl.sx %s0, (%s0, %s1)
190; PIC-NEXT:  .LBB2_4:
191; PIC-NEXT:    ld %s16, 32(, %s11)
192; PIC-NEXT:    ld %s15, 24(, %s11)
193; PIC-NEXT:    b.l.t (, %s10)
194  %2 = add i32 %0, -1
195  %3 = icmp ult i32 %2, 9
196  br i1 %3, label %4, label %13
197
1984:                                                ; preds = %1
199  %5 = trunc i32 %2 to i16
200  %6 = lshr i16 463, %5
201  %7 = and i16 %6, 1
202  %8 = icmp eq i16 %7, 0
203  br i1 %8, label %13, label %9
204
2059:                                                ; preds = %4
206  %10 = sext i32 %2 to i64
207  %11 = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table.br_jt7, i64 0, i64 %10
208  %12 = load i32, i32* %11, align 4
209  ret i32 %12
210
21113:                                               ; preds = %1, %4
212  ret i32 %0
213}
214
215; Function Attrs: norecurse nounwind readnone
216define signext i32 @br_jt8(i32 signext %0) {
217; CHECK-LABEL: br_jt8:
218; CHECK:       # %bb.0:
219; CHECK-NEXT:    and %s0, %s0, (32)0
220; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
221; CHECK-NEXT:    cmpu.w %s2, 8, %s1
222; CHECK-NEXT:    brgt.w 0, %s2, .LBB{{[0-9]+}}_3
223; CHECK-NEXT:  # %bb.1:
224; CHECK-NEXT:    and %s2, %s1, (48)0
225; CHECK-NEXT:    lea %s3, 495
226; CHECK-NEXT:    and %s3, %s3, (32)0
227; CHECK-NEXT:    srl %s2, %s3, %s2
228; CHECK-NEXT:    and %s2, 1, %s2
229; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
230; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
231; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
232; CHECK-NEXT:    b.l.t (, %s10)
233; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
234; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
235; CHECK-NEXT:    sll %s0, %s0, 2
236; CHECK-NEXT:    lea %s1, .Lswitch.table.br_jt8@lo
237; CHECK-NEXT:    and %s1, %s1, (32)0
238; CHECK-NEXT:    lea.sl %s1, .Lswitch.table.br_jt8@hi(, %s1)
239; CHECK-NEXT:    ldl.sx %s0, (%s0, %s1)
240; CHECK-NEXT:    b.l.t (, %s10)
241;
242; PIC-LABEL: br_jt8:
243; PIC:       # %bb.0:
244; PIC-NEXT:    st %s15, 24(, %s11)
245; PIC-NEXT:    st %s16, 32(, %s11)
246; PIC-NEXT:    and %s0, %s0, (32)0
247; PIC-NEXT:    adds.w.sx %s1, -1, %s0
248; PIC-NEXT:    cmpu.w %s2, 8, %s1
249; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
250; PIC-NEXT:    and %s15, %s15, (32)0
251; PIC-NEXT:    sic %s16
252; PIC-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
253; PIC-NEXT:    brgt.w 0, %s2, .LBB3_3
254; PIC-NEXT:  # %bb.1:
255; PIC-NEXT:    and %s2, %s1, (48)0
256; PIC-NEXT:    lea %s3, 495
257; PIC-NEXT:    and %s3, %s3, (32)0
258; PIC-NEXT:    srl %s2, %s3, %s2
259; PIC-NEXT:    and %s2, 1, %s2
260; PIC-NEXT:    brne.w 0, %s2, .LBB3_2
261; PIC-NEXT:  .LBB3_3:
262; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
263; PIC-NEXT:    br.l.t .LBB3_4
264; PIC-NEXT:  .LBB3_2:
265; PIC-NEXT:    adds.w.sx %s0, %s1, (0)1
266; PIC-NEXT:    sll %s0, %s0, 2
267; PIC-NEXT:    lea %s1, .Lswitch.table.br_jt8@gotoff_lo
268; PIC-NEXT:    and %s1, %s1, (32)0
269; PIC-NEXT:    lea.sl %s1, .Lswitch.table.br_jt8@gotoff_hi(%s1, %s15)
270; PIC-NEXT:    ldl.sx %s0, (%s0, %s1)
271; PIC-NEXT:  .LBB3_4:
272; PIC-NEXT:    ld %s16, 32(, %s11)
273; PIC-NEXT:    ld %s15, 24(, %s11)
274; PIC-NEXT:    b.l.t (, %s10)
275  %2 = add i32 %0, -1
276  %3 = icmp ult i32 %2, 9
277  br i1 %3, label %4, label %13
278
2794:                                                ; preds = %1
280  %5 = trunc i32 %2 to i16
281  %6 = lshr i16 495, %5
282  %7 = and i16 %6, 1
283  %8 = icmp eq i16 %7, 0
284  br i1 %8, label %13, label %9
285
2869:                                                ; preds = %4
287  %10 = sext i32 %2 to i64
288  %11 = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table.br_jt8, i64 0, i64 %10
289  %12 = load i32, i32* %11, align 4
290  ret i32 %12
291
29213:                                               ; preds = %1, %4
293  ret i32 %0
294}
295
296; Function Attrs: norecurse nounwind readnone
297define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
298; CHECK-LABEL: br_jt3_m:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    and %s0, %s0, (32)0
301; CHECK-NEXT:    breq.w 1, %s0, .LBB{{[0-9]+}}_1
302; CHECK-NEXT:  # %bb.2:
303; CHECK-NEXT:    breq.w 4, %s0, .LBB{{[0-9]+}}_5
304; CHECK-NEXT:  # %bb.3:
305; CHECK-NEXT:    brne.w 2, %s0, .LBB{{[0-9]+}}_6
306; CHECK-NEXT:  # %bb.4:
307; CHECK-NEXT:    or %s0, 0, (0)1
308; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
309; CHECK-NEXT:    b.l.t (, %s10)
310; CHECK-NEXT:  .LBB{{[0-9]+}}_1:
311; CHECK-NEXT:    or %s0, 3, (0)1
312; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
313; CHECK-NEXT:    b.l.t (, %s10)
314; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
315; CHECK-NEXT:    and %s0, %s1, (32)0
316; CHECK-NEXT:    adds.w.sx %s0, 3, %s0
317; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
318; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
319; CHECK-NEXT:    b.l.t (, %s10)
320;
321; PIC-LABEL: br_jt3_m:
322; PIC:       # %bb.0:
323; PIC-NEXT:    and %s0, %s0, (32)0
324; PIC-NEXT:    breq.w 1, %s0, .LBB4_1
325; PIC-NEXT:  # %bb.2:
326; PIC-NEXT:    breq.w 4, %s0, .LBB4_5
327; PIC-NEXT:  # %bb.3:
328; PIC-NEXT:    brne.w 2, %s0, .LBB4_6
329; PIC-NEXT:  # %bb.4:
330; PIC-NEXT:    or %s0, 0, (0)1
331; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
332; PIC-NEXT:    b.l.t (, %s10)
333; PIC-NEXT:  .LBB4_1:
334; PIC-NEXT:    or %s0, 3, (0)1
335; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
336; PIC-NEXT:    b.l.t (, %s10)
337; PIC-NEXT:  .LBB4_5:
338; PIC-NEXT:    and %s0, %s1, (32)0
339; PIC-NEXT:    adds.w.sx %s0, 3, %s0
340; PIC-NEXT:  .LBB4_6:
341; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
342; PIC-NEXT:    b.l.t (, %s10)
343  switch i32 %0, label %6 [
344    i32 1, label %7
345    i32 2, label %3
346    i32 4, label %4
347  ]
348
3493:                                                ; preds = %2
350  br label %7
351
3524:                                                ; preds = %2
353  %5 = add nsw i32 %1, 3
354  br label %7
355
3566:                                                ; preds = %2
357  br label %7
358
3597:                                                ; preds = %2, %6, %4, %3
360  %8 = phi i32 [ %0, %6 ], [ %5, %4 ], [ 0, %3 ], [ 3, %2 ]
361  ret i32 %8
362}
363
364; Function Attrs: norecurse nounwind readnone
365define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
366; CHECK-LABEL: br_jt4_m:
367; CHECK:       # %bb.0:
368; CHECK-NEXT:    and %s0, %s0, (32)0
369; CHECK-NEXT:    adds.w.sx %s2, -1, %s0
370; CHECK-NEXT:    cmpu.w %s3, 3, %s2
371; CHECK-NEXT:    brgt.w 0, %s3, .LBB{{[0-9]+}}_5
372; CHECK-NEXT:  # %bb.1:
373; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
374; CHECK-NEXT:    sll %s0, %s0, 3
375; CHECK-NEXT:    lea %s2, .LJTI5_0@lo
376; CHECK-NEXT:    and %s2, %s2, (32)0
377; CHECK-NEXT:    lea.sl %s2, .LJTI5_0@hi(, %s2)
378; CHECK-NEXT:    ld %s2, (%s2, %s0)
379; CHECK-NEXT:    or %s0, 3, (0)1
380; CHECK-NEXT:    b.l.t (, %s2)
381; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
382; CHECK-NEXT:    or %s0, 0, (0)1
383; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
384; CHECK-NEXT:    b.l.t (, %s10)
385; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
386; CHECK-NEXT:    or %s0, 4, (0)1
387; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
388; CHECK-NEXT:    b.l.t (, %s10)
389; CHECK-NEXT:  .LBB{{[0-9]+}}_4:
390; CHECK-NEXT:    and %s0, %s1, (32)0
391; CHECK-NEXT:    adds.w.sx %s0, 3, %s0
392; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
393; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
394; CHECK-NEXT:    b.l.t (, %s10)
395;
396; PIC-LABEL: br_jt4_m:
397; PIC:       # %bb.0:
398; PIC-NEXT:    and %s0, %s0, (32)0
399; PIC-NEXT:    brlt.w 2, %s0, .LBB5_4
400; PIC-NEXT:  # %bb.1:
401; PIC-NEXT:    breq.w 1, %s0, .LBB5_8
402; PIC-NEXT:  # %bb.2:
403; PIC-NEXT:    brne.w 2, %s0, .LBB5_7
404; PIC-NEXT:  # %bb.3:
405; PIC-NEXT:    or %s0, 0, (0)1
406; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
407; PIC-NEXT:    b.l.t (, %s10)
408; PIC-NEXT:  .LBB5_4:
409; PIC-NEXT:    breq.w 3, %s0, .LBB5_9
410; PIC-NEXT:  # %bb.5:
411; PIC-NEXT:    brne.w 4, %s0, .LBB5_7
412; PIC-NEXT:  # %bb.6:
413; PIC-NEXT:    and %s0, %s1, (32)0
414; PIC-NEXT:    adds.w.sx %s0, 3, %s0
415; PIC-NEXT:  .LBB5_7:
416; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
417; PIC-NEXT:    b.l.t (, %s10)
418; PIC-NEXT:  .LBB5_8:
419; PIC-NEXT:    or %s0, 3, (0)1
420; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
421; PIC-NEXT:    b.l.t (, %s10)
422; PIC-NEXT:  .LBB5_9:
423; PIC-NEXT:    or %s0, 4, (0)1
424; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
425; PIC-NEXT:    b.l.t (, %s10)
426  switch i32 %0, label %7 [
427    i32 1, label %8
428    i32 2, label %3
429    i32 3, label %4
430    i32 4, label %5
431  ]
432
4333:                                                ; preds = %2
434  br label %8
435
4364:                                                ; preds = %2
437  br label %8
438
4395:                                                ; preds = %2
440  %6 = add nsw i32 %1, 3
441  br label %8
442
4437:                                                ; preds = %2
444  br label %8
445
4468:                                                ; preds = %2, %7, %5, %4, %3
447  %9 = phi i32 [ %0, %7 ], [ %6, %5 ], [ 4, %4 ], [ 0, %3 ], [ 3, %2 ]
448  ret i32 %9
449}
450
451; Function Attrs: norecurse nounwind readnone
452define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
453; CHECK-LABEL: br_jt7_m:
454; CHECK:       # %bb.0:
455; CHECK-NEXT:    and %s2, %s0, (32)0
456; CHECK-NEXT:    adds.w.sx %s0, -1, %s2
457; CHECK-NEXT:    cmpu.w %s3, 8, %s0
458; CHECK-NEXT:    brgt.w 0, %s3, .LBB{{[0-9]+}}_8
459; CHECK-NEXT:  # %bb.1:
460; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
461; CHECK-NEXT:    sll %s0, %s0, 3
462; CHECK-NEXT:    lea %s3, .LJTI6_0@lo
463; CHECK-NEXT:    and %s3, %s3, (32)0
464; CHECK-NEXT:    lea.sl %s3, .LJTI6_0@hi(, %s3)
465; CHECK-NEXT:    ld %s3, (%s3, %s0)
466; CHECK-NEXT:    and %s1, %s1, (32)0
467; CHECK-NEXT:    or %s0, 3, (0)1
468; CHECK-NEXT:    b.l.t (, %s3)
469; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
470; CHECK-NEXT:    or %s0, 0, (0)1
471; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
472; CHECK-NEXT:    b.l.t (, %s10)
473; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
474; CHECK-NEXT:    or %s0, 4, (0)1
475; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
476; CHECK-NEXT:    b.l.t (, %s10)
477; CHECK-NEXT:  .LBB{{[0-9]+}}_4:
478; CHECK-NEXT:    adds.w.sx %s0, 3, %s1
479; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
480; CHECK-NEXT:    b.l.t (, %s10)
481; CHECK-NEXT:  .LBB{{[0-9]+}}_8:
482; CHECK-NEXT:    or %s0, 0, %s2
483; CHECK-NEXT:  .LBB{{[0-9]+}}_9:
484; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
485; CHECK-NEXT:    b.l.t (, %s10)
486; CHECK-NEXT:  .LBB{{[0-9]+}}_7:
487; CHECK-NEXT:    or %s0, 11, (0)1
488; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
489; CHECK-NEXT:    b.l.t (, %s10)
490; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
491; CHECK-NEXT:    or %s0, 10, (0)1
492; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
493; CHECK-NEXT:    b.l.t (, %s10)
494; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
495; CHECK-NEXT:    adds.w.sx %s0, -2, %s1
496; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
497; CHECK-NEXT:    b.l.t (, %s10)
498;
499; PIC-LABEL: br_jt7_m:
500; PIC:       # %bb.0:
501; PIC-NEXT:    and %s0, %s0, (32)0
502; PIC-NEXT:    brge.w 3, %s0, .LBB6_1
503; PIC-NEXT:  # %bb.6:
504; PIC-NEXT:    brlt.w 7, %s0, .LBB6_10
505; PIC-NEXT:  # %bb.7:
506; PIC-NEXT:    and %s1, %s1, (32)0
507; PIC-NEXT:    breq.w 4, %s0, .LBB6_14
508; PIC-NEXT:  # %bb.8:
509; PIC-NEXT:    brne.w 7, %s0, .LBB6_16
510; PIC-NEXT:  # %bb.9:
511; PIC-NEXT:    adds.w.sx %s0, -2, %s1
512; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
513; PIC-NEXT:    b.l.t (, %s10)
514; PIC-NEXT:  .LBB6_1:
515; PIC-NEXT:    breq.w 1, %s0, .LBB6_2
516; PIC-NEXT:  # %bb.3:
517; PIC-NEXT:    breq.w 2, %s0, .LBB6_13
518; PIC-NEXT:  # %bb.4:
519; PIC-NEXT:    brne.w 3, %s0, .LBB6_16
520; PIC-NEXT:  # %bb.5:
521; PIC-NEXT:    or %s0, 4, (0)1
522; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
523; PIC-NEXT:    b.l.t (, %s10)
524; PIC-NEXT:  .LBB6_10:
525; PIC-NEXT:    breq.w 8, %s0, .LBB6_15
526; PIC-NEXT:  # %bb.11:
527; PIC-NEXT:    brne.w 9, %s0, .LBB6_16
528; PIC-NEXT:  # %bb.12:
529; PIC-NEXT:    or %s0, 10, (0)1
530; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
531; PIC-NEXT:    b.l.t (, %s10)
532; PIC-NEXT:  .LBB6_14:
533; PIC-NEXT:    adds.w.sx %s0, 3, %s1
534; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
535; PIC-NEXT:    b.l.t (, %s10)
536; PIC-NEXT:  .LBB6_2:
537; PIC-NEXT:    or %s0, 3, (0)1
538; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
539; PIC-NEXT:    b.l.t (, %s10)
540; PIC-NEXT:  .LBB6_15:
541; PIC-NEXT:    or %s0, 11, (0)1
542; PIC-NEXT:  .LBB6_16:
543; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
544; PIC-NEXT:    b.l.t (, %s10)
545; PIC-NEXT:  .LBB6_13:
546; PIC-NEXT:    or %s0, 0, (0)1
547; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
548; PIC-NEXT:    b.l.t (, %s10)
549  switch i32 %0, label %11 [
550    i32 1, label %12
551    i32 2, label %3
552    i32 3, label %4
553    i32 4, label %5
554    i32 7, label %7
555    i32 9, label %9
556    i32 8, label %10
557  ]
558
5593:                                                ; preds = %2
560  br label %12
561
5624:                                                ; preds = %2
563  br label %12
564
5655:                                                ; preds = %2
566  %6 = add nsw i32 %1, 3
567  br label %12
568
5697:                                                ; preds = %2
570  %8 = add nsw i32 %1, -2
571  br label %12
572
5739:                                                ; preds = %2
574  br label %12
575
57610:                                               ; preds = %2
577  br label %12
578
57911:                                               ; preds = %2
580  br label %12
581
58212:                                               ; preds = %2, %11, %10, %9, %7, %5, %4, %3
583  %13 = phi i32 [ %0, %11 ], [ 11, %10 ], [ 10, %9 ], [ %8, %7 ], [ %6, %5 ], [ 4, %4 ], [ 0, %3 ], [ 3, %2 ]
584  ret i32 %13
585}
586
587; Function Attrs: norecurse nounwind readnone
588define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
589; CHECK-LABEL: br_jt8_m:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    and %s2, %s0, (32)0
592; CHECK-NEXT:    adds.w.sx %s0, -1, %s2
593; CHECK-NEXT:    cmpu.w %s3, 8, %s0
594; CHECK-NEXT:    brgt.w 0, %s3, .LBB{{[0-9]+}}_9
595; CHECK-NEXT:  # %bb.1:
596; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
597; CHECK-NEXT:    sll %s0, %s0, 3
598; CHECK-NEXT:    lea %s3, .LJTI7_0@lo
599; CHECK-NEXT:    and %s3, %s3, (32)0
600; CHECK-NEXT:    lea.sl %s3, .LJTI7_0@hi(, %s3)
601; CHECK-NEXT:    ld %s3, (%s3, %s0)
602; CHECK-NEXT:    and %s1, %s1, (32)0
603; CHECK-NEXT:    or %s0, 3, (0)1
604; CHECK-NEXT:    b.l.t (, %s3)
605; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
606; CHECK-NEXT:    or %s0, 0, (0)1
607; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
608; CHECK-NEXT:    b.l.t (, %s10)
609; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
610; CHECK-NEXT:    or %s0, 4, (0)1
611; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
612; CHECK-NEXT:    b.l.t (, %s10)
613; CHECK-NEXT:  .LBB{{[0-9]+}}_4:
614; CHECK-NEXT:    adds.w.sx %s0, 3, %s1
615; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
616; CHECK-NEXT:    b.l.t (, %s10)
617; CHECK-NEXT:  .LBB{{[0-9]+}}_9:
618; CHECK-NEXT:    or %s0, 0, %s2
619; CHECK-NEXT:  .LBB{{[0-9]+}}_10:
620; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
621; CHECK-NEXT:    b.l.t (, %s10)
622; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
623; CHECK-NEXT:    adds.w.sx %s0, -5, %s1
624; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
625; CHECK-NEXT:    b.l.t (, %s10)
626; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
627; CHECK-NEXT:    adds.w.sx %s0, -2, %s1
628; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
629; CHECK-NEXT:    b.l.t (, %s10)
630; CHECK-NEXT:  .LBB{{[0-9]+}}_8:
631; CHECK-NEXT:    or %s0, 11, (0)1
632; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
633; CHECK-NEXT:    b.l.t (, %s10)
634; CHECK-NEXT:  .LBB{{[0-9]+}}_7:
635; CHECK-NEXT:    or %s0, 10, (0)1
636; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
637; CHECK-NEXT:    b.l.t (, %s10)
638;
639; PIC-LABEL: br_jt8_m:
640; PIC:       # %bb.0:
641; PIC-NEXT:    st %s15, 24(, %s11)
642; PIC-NEXT:    st %s16, 32(, %s11)
643; PIC-NEXT:    and %s2, %s0, (32)0
644; PIC-NEXT:    adds.w.sx %s0, -1, %s2
645; PIC-NEXT:    cmpu.w %s3, 8, %s0
646; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
647; PIC-NEXT:    and %s15, %s15, (32)0
648; PIC-NEXT:    sic %s16
649; PIC-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
650; PIC-NEXT:    brgt.w 0, %s3, .LBB7_9
651; PIC-NEXT:  # %bb.1:
652; PIC-NEXT:    and %s1, %s1, (32)0
653; PIC-NEXT:    adds.w.zx %s0, %s0, (0)1
654; PIC-NEXT:    sll %s0, %s0, 2
655; PIC-NEXT:    lea %s3, .LJTI7_0@gotoff_lo
656; PIC-NEXT:    and %s3, %s3, (32)0
657; PIC-NEXT:    lea.sl %s3, .LJTI7_0@gotoff_hi(%s3, %s15)
658; PIC-NEXT:    ldl.sx %s0, (%s3, %s0)
659; PIC-NEXT:    lea %s3, br_jt8_m@gotoff_lo
660; PIC-NEXT:    and %s3, %s3, (32)0
661; PIC-NEXT:    lea.sl %s3, br_jt8_m@gotoff_hi(%s3, %s15)
662; PIC-NEXT:    adds.l %s3, %s0, %s3
663; PIC-NEXT:    or %s0, 3, (0)1
664; PIC-NEXT:    b.l.t (, %s3)
665; PIC-NEXT:  .LBB7_2:
666; PIC-NEXT:    or %s0, 0, (0)1
667; PIC-NEXT:    br.l.t .LBB7_10
668; PIC-NEXT:  .LBB7_3:
669; PIC-NEXT:    or %s0, 4, (0)1
670; PIC-NEXT:    br.l.t .LBB7_10
671; PIC-NEXT:  .LBB7_4:
672; PIC-NEXT:    adds.w.sx %s0, 3, %s1
673; PIC-NEXT:    br.l.t .LBB7_10
674; PIC-NEXT:  .LBB7_9:
675; PIC-NEXT:    or %s0, 0, %s2
676; PIC-NEXT:    br.l.t .LBB7_10
677; PIC-NEXT:  .LBB7_5:
678; PIC-NEXT:    adds.w.sx %s0, -5, %s1
679; PIC-NEXT:    br.l.t .LBB7_10
680; PIC-NEXT:  .LBB7_6:
681; PIC-NEXT:    adds.w.sx %s0, -2, %s1
682; PIC-NEXT:    br.l.t .LBB7_10
683; PIC-NEXT:  .LBB7_8:
684; PIC-NEXT:    or %s0, 11, (0)1
685; PIC-NEXT:    br.l.t .LBB7_10
686; PIC-NEXT:  .LBB7_7:
687; PIC-NEXT:    or %s0, 10, (0)1
688; PIC-NEXT:  .LBB7_10:
689; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
690; PIC-NEXT:    ld %s16, 32(, %s11)
691; PIC-NEXT:    ld %s15, 24(, %s11)
692; PIC-NEXT:    b.l.t (, %s10)
693  switch i32 %0, label %13 [
694    i32 1, label %14
695    i32 2, label %3
696    i32 3, label %4
697    i32 4, label %5
698    i32 6, label %7
699    i32 7, label %9
700    i32 9, label %11
701    i32 8, label %12
702  ]
703
7043:                                                ; preds = %2
705  br label %14
706
7074:                                                ; preds = %2
708  br label %14
709
7105:                                                ; preds = %2
711  %6 = add nsw i32 %1, 3
712  br label %14
713
7147:                                                ; preds = %2
715  %8 = add nsw i32 %1, -5
716  br label %14
717
7189:                                                ; preds = %2
719  %10 = add nsw i32 %1, -2
720  br label %14
721
72211:                                               ; preds = %2
723  br label %14
724
72512:                                               ; preds = %2
726  br label %14
727
72813:                                               ; preds = %2
729  br label %14
730
73114:                                               ; preds = %2, %13, %12, %11, %9, %7, %5, %4, %3
732  %15 = phi i32 [ %0, %13 ], [ 11, %12 ], [ 10, %11 ], [ %10, %9 ], [ %8, %7 ], [ %6, %5 ], [ 4, %4 ], [ 0, %3 ], [ 3, %2 ]
733  ret i32 %15
734}
735