1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test vector equivalence intrinsic instructions 4;;; 5;;; Note: 6;;; We test VEQV*vvl, VEQV*vvl_v, VEQV*rvl, VEQV*rvl_v, VEQV*vvml_v, 7;;; VEQV*rvml_v, PVEQV*vvl, PVEQV*vvl_v, PVEQV*rvl, PVEQV*rvl_v, PVEQV*vvml_v, 8;;; and PVEQV*rvml_v instructions. 9 10; Function Attrs: nounwind readnone 11define fastcc <256 x double> @veqv_vvvl(<256 x double> %0, <256 x double> %1) { 12; CHECK-LABEL: veqv_vvvl: 13; CHECK: # %bb.0: 14; CHECK-NEXT: lea %s0, 256 15; CHECK-NEXT: lvl %s0 16; CHECK-NEXT: veqv %v0, %v0, %v1 17; CHECK-NEXT: b.l.t (, %s10) 18 %3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 19 ret <256 x double> %3 20} 21 22; Function Attrs: nounwind readnone 23declare <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double>, <256 x double>, i32) 24 25; Function Attrs: nounwind readnone 26define fastcc <256 x double> @veqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 27; CHECK-LABEL: veqv_vvvvl: 28; CHECK: # %bb.0: 29; CHECK-NEXT: lea %s0, 128 30; CHECK-NEXT: lvl %s0 31; CHECK-NEXT: veqv %v2, %v0, %v1 32; CHECK-NEXT: lea %s16, 256 33; CHECK-NEXT: lvl %s16 34; CHECK-NEXT: vor %v0, (0)1, %v2 35; CHECK-NEXT: b.l.t (, %s10) 36 %4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 37 ret <256 x double> %4 38} 39 40; Function Attrs: nounwind readnone 41declare <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 42 43; Function Attrs: nounwind readnone 44define fastcc <256 x double> @veqv_vsvl(i64 %0, <256 x double> %1) { 45; CHECK-LABEL: veqv_vsvl: 46; CHECK: # %bb.0: 47; CHECK-NEXT: lea %s1, 256 48; CHECK-NEXT: lvl %s1 49; CHECK-NEXT: veqv %v0, %s0, %v0 50; CHECK-NEXT: b.l.t (, %s10) 51 %3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvl(i64 %0, <256 x double> %1, i32 256) 52 ret <256 x double> %3 53} 54 55; Function Attrs: nounwind readnone 56declare <256 x double> @llvm.ve.vl.veqv.vsvl(i64, <256 x double>, i32) 57 58; Function Attrs: nounwind readnone 59define fastcc <256 x double> @veqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 60; CHECK-LABEL: veqv_vsvvl: 61; CHECK: # %bb.0: 62; CHECK-NEXT: lea %s1, 128 63; CHECK-NEXT: lvl %s1 64; CHECK-NEXT: veqv %v1, %s0, %v0 65; CHECK-NEXT: lea %s16, 256 66; CHECK-NEXT: lvl %s16 67; CHECK-NEXT: vor %v0, (0)1, %v1 68; CHECK-NEXT: b.l.t (, %s10) 69 %4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 70 ret <256 x double> %4 71} 72 73; Function Attrs: nounwind readnone 74declare <256 x double> @llvm.ve.vl.veqv.vsvvl(i64, <256 x double>, <256 x double>, i32) 75 76; Function Attrs: nounwind readnone 77define fastcc <256 x double> @veqv_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 78; CHECK-LABEL: veqv_vvvmvl: 79; CHECK: # %bb.0: 80; CHECK-NEXT: lea %s0, 128 81; CHECK-NEXT: lvl %s0 82; CHECK-NEXT: veqv %v2, %v0, %v1, %vm1 83; CHECK-NEXT: lea %s16, 256 84; CHECK-NEXT: lvl %s16 85; CHECK-NEXT: vor %v0, (0)1, %v2 86; CHECK-NEXT: b.l.t (, %s10) 87 %5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 88 ret <256 x double> %5 89} 90 91; Function Attrs: nounwind readnone 92declare <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 93 94; Function Attrs: nounwind readnone 95define fastcc <256 x double> @veqv_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 96; CHECK-LABEL: veqv_vsvmvl: 97; CHECK: # %bb.0: 98; CHECK-NEXT: lea %s1, 128 99; CHECK-NEXT: lvl %s1 100; CHECK-NEXT: veqv %v1, %s0, %v0, %vm1 101; CHECK-NEXT: lea %s16, 256 102; CHECK-NEXT: lvl %s16 103; CHECK-NEXT: vor %v0, (0)1, %v1 104; CHECK-NEXT: b.l.t (, %s10) 105 %5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 106 ret <256 x double> %5 107} 108 109; Function Attrs: nounwind readnone 110declare <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) 111 112; Function Attrs: nounwind readnone 113define fastcc <256 x double> @pveqv_vvvl(<256 x double> %0, <256 x double> %1) { 114; CHECK-LABEL: pveqv_vvvl: 115; CHECK: # %bb.0: 116; CHECK-NEXT: lea %s0, 256 117; CHECK-NEXT: lvl %s0 118; CHECK-NEXT: pveqv %v0, %v0, %v1 119; CHECK-NEXT: b.l.t (, %s10) 120 %3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 121 ret <256 x double> %3 122} 123 124; Function Attrs: nounwind readnone 125declare <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double>, <256 x double>, i32) 126 127; Function Attrs: nounwind readnone 128define fastcc <256 x double> @pveqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 129; CHECK-LABEL: pveqv_vvvvl: 130; CHECK: # %bb.0: 131; CHECK-NEXT: lea %s0, 128 132; CHECK-NEXT: lvl %s0 133; CHECK-NEXT: pveqv %v2, %v0, %v1 134; CHECK-NEXT: lea %s16, 256 135; CHECK-NEXT: lvl %s16 136; CHECK-NEXT: vor %v0, (0)1, %v2 137; CHECK-NEXT: b.l.t (, %s10) 138 %4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 139 ret <256 x double> %4 140} 141 142; Function Attrs: nounwind readnone 143declare <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 144 145; Function Attrs: nounwind readnone 146define fastcc <256 x double> @pveqv_vsvl(i64 %0, <256 x double> %1) { 147; CHECK-LABEL: pveqv_vsvl: 148; CHECK: # %bb.0: 149; CHECK-NEXT: lea %s1, 256 150; CHECK-NEXT: lvl %s1 151; CHECK-NEXT: pveqv %v0, %s0, %v0 152; CHECK-NEXT: b.l.t (, %s10) 153 %3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvl(i64 %0, <256 x double> %1, i32 256) 154 ret <256 x double> %3 155} 156 157; Function Attrs: nounwind readnone 158declare <256 x double> @llvm.ve.vl.pveqv.vsvl(i64, <256 x double>, i32) 159 160; Function Attrs: nounwind readnone 161define fastcc <256 x double> @pveqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 162; CHECK-LABEL: pveqv_vsvvl: 163; CHECK: # %bb.0: 164; CHECK-NEXT: lea %s1, 128 165; CHECK-NEXT: lvl %s1 166; CHECK-NEXT: pveqv %v1, %s0, %v0 167; CHECK-NEXT: lea %s16, 256 168; CHECK-NEXT: lvl %s16 169; CHECK-NEXT: vor %v0, (0)1, %v1 170; CHECK-NEXT: b.l.t (, %s10) 171 %4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 172 ret <256 x double> %4 173} 174 175; Function Attrs: nounwind readnone 176declare <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64, <256 x double>, <256 x double>, i32) 177 178; Function Attrs: nounwind readnone 179define fastcc <256 x double> @pveqv_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { 180; CHECK-LABEL: pveqv_vvvMvl: 181; CHECK: # %bb.0: 182; CHECK-NEXT: lea %s0, 128 183; CHECK-NEXT: lvl %s0 184; CHECK-NEXT: pveqv %v2, %v0, %v1, %vm2 185; CHECK-NEXT: lea %s16, 256 186; CHECK-NEXT: lvl %s16 187; CHECK-NEXT: vor %v0, (0)1, %v2 188; CHECK-NEXT: b.l.t (, %s10) 189 %5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) 190 ret <256 x double> %5 191} 192 193; Function Attrs: nounwind readnone 194declare <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32) 195 196; Function Attrs: nounwind readnone 197define fastcc <256 x double> @pveqv_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { 198; CHECK-LABEL: pveqv_vsvMvl: 199; CHECK: # %bb.0: 200; CHECK-NEXT: lea %s1, 128 201; CHECK-NEXT: lvl %s1 202; CHECK-NEXT: pveqv %v1, %s0, %v0, %vm2 203; CHECK-NEXT: lea %s16, 256 204; CHECK-NEXT: lvl %s16 205; CHECK-NEXT: vor %v0, (0)1, %v1 206; CHECK-NEXT: b.l.t (, %s10) 207 %5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) 208 ret <256 x double> %5 209} 210 211; Function Attrs: nounwind readnone 212declare <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32) 213