1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test vector floating reciprocal intrinsic instructions
4;;;
5;;; Note:
6;;;   We test VRCP*vl, VRCP*vl_v, PVRCP*vl, and PVRCP*vl_v instructions.
7
8; Function Attrs: nounwind readnone
9define fastcc <256 x double> @vrcpd_vvl(<256 x double> %0) {
10; CHECK-LABEL: vrcpd_vvl:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    lea %s0, 256
13; CHECK-NEXT:    lvl %s0
14; CHECK-NEXT:    vrcp.d %v0, %v0
15; CHECK-NEXT:    b.l.t (, %s10)
16  %2 = tail call fast <256 x double> @llvm.ve.vl.vrcpd.vvl(<256 x double> %0, i32 256)
17  ret <256 x double> %2
18}
19
20; Function Attrs: nounwind readnone
21declare <256 x double> @llvm.ve.vl.vrcpd.vvl(<256 x double>, i32)
22
23; Function Attrs: nounwind readnone
24define fastcc <256 x double> @vrcpd_vvvl(<256 x double> %0, <256 x double> %1) {
25; CHECK-LABEL: vrcpd_vvvl:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    lea %s0, 128
28; CHECK-NEXT:    lvl %s0
29; CHECK-NEXT:    vrcp.d %v1, %v0
30; CHECK-NEXT:    lea %s16, 256
31; CHECK-NEXT:    lvl %s16
32; CHECK-NEXT:    vor %v0, (0)1, %v1
33; CHECK-NEXT:    b.l.t (, %s10)
34  %3 = tail call fast <256 x double> @llvm.ve.vl.vrcpd.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
35  ret <256 x double> %3
36}
37
38; Function Attrs: nounwind readnone
39declare <256 x double> @llvm.ve.vl.vrcpd.vvvl(<256 x double>, <256 x double>, i32)
40
41; Function Attrs: nounwind readnone
42define fastcc <256 x double> @vrcps_vvl(<256 x double> %0) {
43; CHECK-LABEL: vrcps_vvl:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    lea %s0, 256
46; CHECK-NEXT:    lvl %s0
47; CHECK-NEXT:    vrcp.s %v0, %v0
48; CHECK-NEXT:    b.l.t (, %s10)
49  %2 = tail call fast <256 x double> @llvm.ve.vl.vrcps.vvl(<256 x double> %0, i32 256)
50  ret <256 x double> %2
51}
52
53; Function Attrs: nounwind readnone
54declare <256 x double> @llvm.ve.vl.vrcps.vvl(<256 x double>, i32)
55
56; Function Attrs: nounwind readnone
57define fastcc <256 x double> @vrcps_vvvl(<256 x double> %0, <256 x double> %1) {
58; CHECK-LABEL: vrcps_vvvl:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    lea %s0, 128
61; CHECK-NEXT:    lvl %s0
62; CHECK-NEXT:    vrcp.s %v1, %v0
63; CHECK-NEXT:    lea %s16, 256
64; CHECK-NEXT:    lvl %s16
65; CHECK-NEXT:    vor %v0, (0)1, %v1
66; CHECK-NEXT:    b.l.t (, %s10)
67  %3 = tail call fast <256 x double> @llvm.ve.vl.vrcps.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
68  ret <256 x double> %3
69}
70
71; Function Attrs: nounwind readnone
72declare <256 x double> @llvm.ve.vl.vrcps.vvvl(<256 x double>, <256 x double>, i32)
73
74; Function Attrs: nounwind readnone
75define fastcc <256 x double> @pvrcp_vvl(<256 x double> %0) {
76; CHECK-LABEL: pvrcp_vvl:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    lea %s0, 256
79; CHECK-NEXT:    lvl %s0
80; CHECK-NEXT:    pvrcp %v0, %v0
81; CHECK-NEXT:    b.l.t (, %s10)
82  %2 = tail call fast <256 x double> @llvm.ve.vl.pvrcp.vvl(<256 x double> %0, i32 256)
83  ret <256 x double> %2
84}
85
86; Function Attrs: nounwind readnone
87declare <256 x double> @llvm.ve.vl.pvrcp.vvl(<256 x double>, i32)
88
89; Function Attrs: nounwind readnone
90define fastcc <256 x double> @pvrcp_vvvl(<256 x double> %0, <256 x double> %1) {
91; CHECK-LABEL: pvrcp_vvvl:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    lea %s0, 128
94; CHECK-NEXT:    lvl %s0
95; CHECK-NEXT:    pvrcp %v1, %v0
96; CHECK-NEXT:    lea %s16, 256
97; CHECK-NEXT:    lvl %s16
98; CHECK-NEXT:    vor %v0, (0)1, %v1
99; CHECK-NEXT:    b.l.t (, %s10)
100  %3 = tail call fast <256 x double> @llvm.ve.vl.pvrcp.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
101  ret <256 x double> %3
102}
103
104; Function Attrs: nounwind readnone
105declare <256 x double> @llvm.ve.vl.pvrcp.vvvl(<256 x double>, <256 x double>, i32)
106