1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3; rdar://7527734
4
5define i32 @test1(i32 %x) nounwind ssp {
6; CHECK-LABEL: test1:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
9; CHECK-NEXT:    shll $5, %edi
10; CHECK-NEXT:    leal 3(%rdi), %eax
11; CHECK-NEXT:    retq
12  %t0 = shl i32 %x, 5
13  %t1 = or i32 %t0, 3
14  ret i32 %t1
15}
16
17; This test no longer requires or to be converted to 3 addr form because we are
18; are able to use a zero extend instead of an 'and' which gives the register
19; allocator freedom.
20define i64 @test2(i8 %A, i8 %B) nounwind {
21; CHECK-LABEL: test2:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
24; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
25; CHECK-NEXT:    shll $4, %edi
26; CHECK-NEXT:    andl $48, %edi
27; CHECK-NEXT:    movzbl %sil, %eax
28; CHECK-NEXT:    shrq $4, %rax
29; CHECK-NEXT:    orq %rdi, %rax
30; CHECK-NEXT:    retq
31  %C = zext i8 %A to i64
32  %D = shl i64 %C, 4
33  %E = and i64 %D, 48
34  %F = zext i8 %B to i64
35  %G = lshr i64 %F, 4
36  %H = or i64 %G, %E
37  ret i64 %H
38}
39
40;; Test that OR is only emitted as LEA, not as ADD.
41
42; No reason to emit an add here, should be an or.
43define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
44; CHECK-LABEL: test3:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    shll $5, %edi
47; CHECK-NEXT:    orl $3, %edi
48; CHECK-NEXT:    movl %edi, (%rsi)
49; CHECK-NEXT:    retq
50  %t0 = shl i32 %x, 5
51  %t1 = or i32 %t0, 3
52  store i32 %t1, i32* %P
53  ret void
54}
55
56define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {
57; CHECK-LABEL: test4:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
60; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
61; CHECK-NEXT:    andl $6, %edi
62; CHECK-NEXT:    andl $16, %esi
63; CHECK-NEXT:    leal (%rsi,%rdi), %eax
64; CHECK-NEXT:    retq
65  %and = and i32 %a, 6
66  %and2 = and i32 %b, 16
67  %or = or i32 %and2, %and
68  ret i32 %or
69}
70
71define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp {
72; CHECK-LABEL: test5:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    andl $6, %edi
75; CHECK-NEXT:    andl $16, %esi
76; CHECK-NEXT:    orl %edi, %esi
77; CHECK-NEXT:    movl %esi, (%rdx)
78; CHECK-NEXT:    retq
79  %and = and i32 %a, 6
80  %and2 = and i32 %b, 16
81  %or = or i32 %and2, %and
82  store i32 %or, i32* %P, align 4
83  ret void
84}
85
86