1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
3
4--- |
5  define i64 @test_sext_i1(i8 %a) {
6    %val = trunc i8 %a to i1
7    %r = sext i1 %val to i64
8    ret i64 %r
9  }
10
11  define i64 @test_sext_i8(i8 %val) {
12    %r = sext i8 %val to i64
13    ret i64 %r
14  }
15
16  define i64 @test_sext_i16(i16 %val) {
17    %r = sext i16 %val to i64
18    ret i64 %r
19  }
20
21  define i64 @test_sext_i32(i32 %val) {
22    %r = sext i32 %val to i64
23    ret i64 %r
24  }
25
26  define i64 @test_zext_i1(i8 %a) {
27    %val = trunc i8 %a to i1
28    %r = zext i1 %val to i64
29    ret i64 %r
30  }
31
32  define i64 @test_zext_i8(i8 %val) {
33    %r = zext i8 %val to i64
34    ret i64 %r
35  }
36
37  define i64 @test_zext_i16(i16 %val) {
38    %r = zext i16 %val to i64
39    ret i64 %r
40  }
41
42  define i64 @test_zext_i32(i32 %val) {
43    %r = zext i32 %val to i64
44    ret i64 %r
45  }
46
47  define void @test_anyext_i1(i8 %a) {
48    ret void
49  }
50
51  define void @test_anyext_i8(i8 %val) {
52    ret void
53  }
54
55  define void @test_anyext_i16(i16 %val) {
56    ret void
57  }
58
59  define void @test_anyext_i32(i32 %val) {
60    ret void
61  }
62
63
64...
65---
66name:            test_sext_i1
67alignment:       16
68legalized:       false
69regBankSelected: false
70registers:
71  - { id: 0, class: _ }
72  - { id: 1, class: _ }
73  - { id: 2, class: _ }
74body:             |
75  bb.1 (%ir-block.0):
76    liveins: $edi
77
78    ; CHECK-LABEL: name: test_sext_i1
79    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
80    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
81    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
82    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s8)
83    ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
84    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s8)
85    ; CHECK: $rax = COPY [[ASHR]](s64)
86    ; CHECK: RET 0, implicit $rax
87    %0(s8) = COPY $dil
88    %1(s1) = G_TRUNC %0(s8)
89    %2(s64) = G_SEXT %1(s1)
90    $rax = COPY %2(s64)
91    RET 0, implicit $rax
92
93...
94---
95name:            test_sext_i8
96alignment:       16
97legalized:       false
98regBankSelected: false
99registers:
100  - { id: 0, class: _ }
101  - { id: 1, class: _ }
102body:             |
103  bb.1 (%ir-block.0):
104    liveins: $edi
105
106    ; CHECK-LABEL: name: test_sext_i8
107    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
108    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
109    ; CHECK: $rax = COPY [[SEXT]](s64)
110    ; CHECK: RET 0, implicit $rax
111    %0(s8) = COPY $dil
112    %1(s64) = G_SEXT %0(s8)
113    $rax = COPY %1(s64)
114    RET 0, implicit $rax
115
116...
117---
118name:            test_sext_i16
119alignment:       16
120legalized:       false
121regBankSelected: false
122registers:
123  - { id: 0, class: _ }
124  - { id: 1, class: _ }
125body:             |
126  bb.1 (%ir-block.0):
127    liveins: $edi
128
129    ; CHECK-LABEL: name: test_sext_i16
130    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
131    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
132    ; CHECK: $rax = COPY [[SEXT]](s64)
133    ; CHECK: RET 0, implicit $rax
134    %0(s16) = COPY $di
135    %1(s64) = G_SEXT %0(s16)
136    $rax = COPY %1(s64)
137    RET 0, implicit $rax
138
139...
140---
141name:            test_sext_i32
142alignment:       16
143legalized:       false
144regBankSelected: false
145registers:
146  - { id: 0, class: _ }
147  - { id: 1, class: _ }
148body:             |
149  bb.1 (%ir-block.0):
150    liveins: $edi
151
152    ; CHECK-LABEL: name: test_sext_i32
153    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
154    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
155    ; CHECK: $rax = COPY [[SEXT]](s64)
156    ; CHECK: RET 0, implicit $rax
157    %0(s32) = COPY $edi
158    %1(s64) = G_SEXT %0(s32)
159    $rax = COPY %1(s64)
160    RET 0, implicit $rax
161
162...
163---
164name:            test_zext_i1
165alignment:       16
166legalized:       false
167regBankSelected: false
168registers:
169  - { id: 0, class: _ }
170  - { id: 1, class: _ }
171  - { id: 2, class: _ }
172body:             |
173  bb.1 (%ir-block.0):
174    liveins: $edi
175
176    ; CHECK-LABEL: name: test_zext_i1
177    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
178    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
179    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
180    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
181    ; CHECK: $rax = COPY [[AND]](s64)
182    ; CHECK: RET 0, implicit $rax
183    %0(s8) = COPY $dil
184    %1(s1) = G_TRUNC %0(s8)
185    %2(s64) = G_ZEXT %1(s1)
186    $rax = COPY %2(s64)
187    RET 0, implicit $rax
188
189...
190---
191name:            test_zext_i8
192alignment:       16
193legalized:       false
194regBankSelected: false
195registers:
196  - { id: 0, class: _ }
197  - { id: 1, class: _ }
198body:             |
199  bb.1 (%ir-block.0):
200    liveins: $edi
201
202    ; CHECK-LABEL: name: test_zext_i8
203    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
204    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s8)
205    ; CHECK: $rax = COPY [[ZEXT]](s64)
206    ; CHECK: RET 0, implicit $rax
207    %0(s8) = COPY $dil
208    %1(s64) = G_ZEXT %0(s8)
209    $rax = COPY %1(s64)
210    RET 0, implicit $rax
211
212...
213---
214name:            test_zext_i16
215alignment:       16
216legalized:       false
217regBankSelected: false
218registers:
219  - { id: 0, class: _ }
220  - { id: 1, class: _ }
221body:             |
222  bb.1 (%ir-block.0):
223    liveins: $edi
224
225    ; CHECK-LABEL: name: test_zext_i16
226    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
227    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
228    ; CHECK: $rax = COPY [[ZEXT]](s64)
229    ; CHECK: RET 0, implicit $rax
230    %0(s16) = COPY $di
231    %1(s64) = G_ZEXT %0(s16)
232    $rax = COPY %1(s64)
233    RET 0, implicit $rax
234
235...
236---
237name:            test_zext_i32
238alignment:       16
239legalized:       false
240regBankSelected: false
241registers:
242  - { id: 0, class: _ }
243  - { id: 1, class: _ }
244body:             |
245  bb.1 (%ir-block.0):
246    liveins: $edi
247
248    ; CHECK-LABEL: name: test_zext_i32
249    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
250    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
251    ; CHECK: $rax = COPY [[ZEXT]](s64)
252    ; CHECK: RET 0, implicit $rax
253    %0(s32) = COPY $edi
254    %1(s64) = G_ZEXT %0(s32)
255    $rax = COPY %1(s64)
256    RET 0, implicit $rax
257
258...
259---
260name:            test_anyext_i1
261alignment:       16
262legalized:       false
263regBankSelected: false
264registers:
265  - { id: 0, class: _ }
266  - { id: 1, class: _ }
267  - { id: 2, class: _ }
268body:             |
269  bb.1 (%ir-block.0):
270    liveins: $edi
271
272    ; CHECK-LABEL: name: test_anyext_i1
273    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
274    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
275    ; CHECK: $rax = COPY [[ANYEXT]](s64)
276    ; CHECK: RET 0, implicit $rax
277    %0(s8) = COPY $dil
278    %1(s1) = G_TRUNC %0(s8)
279    %2(s64) = G_ANYEXT %1(s1)
280    $rax = COPY %2(s64)
281    RET 0, implicit $rax
282
283...
284---
285name:            test_anyext_i8
286alignment:       16
287legalized:       false
288regBankSelected: false
289registers:
290  - { id: 0, class: _ }
291  - { id: 1, class: _ }
292body:             |
293  bb.1 (%ir-block.0):
294    liveins: $edi
295
296    ; CHECK-LABEL: name: test_anyext_i8
297    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
298    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
299    ; CHECK: $rax = COPY [[ANYEXT]](s64)
300    ; CHECK: RET 0, implicit $rax
301    %0(s8) = COPY $dil
302    %1(s64) = G_ANYEXT %0(s8)
303    $rax = COPY %1(s64)
304    RET 0, implicit $rax
305
306...
307---
308name:            test_anyext_i16
309alignment:       16
310legalized:       false
311regBankSelected: false
312registers:
313  - { id: 0, class: _ }
314  - { id: 1, class: _ }
315body:             |
316  bb.1 (%ir-block.0):
317    liveins: $edi
318
319    ; CHECK-LABEL: name: test_anyext_i16
320    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
321    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
322    ; CHECK: $rax = COPY [[ANYEXT]](s64)
323    ; CHECK: RET 0, implicit $rax
324    %0(s16) = COPY $di
325    %1(s64) = G_ANYEXT %0(s16)
326    $rax = COPY %1(s64)
327    RET 0, implicit $rax
328
329...
330---
331name:            test_anyext_i32
332alignment:       16
333legalized:       false
334regBankSelected: false
335registers:
336  - { id: 0, class: _ }
337  - { id: 1, class: _ }
338body:             |
339  bb.1 (%ir-block.0):
340    liveins: $edi
341
342    ; CHECK-LABEL: name: test_anyext_i32
343    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
344    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
345    ; CHECK: $rax = COPY [[ANYEXT]](s64)
346    ; CHECK: RET 0, implicit $rax
347    %0(s32) = COPY $edi
348    %1(s64) = G_ANYEXT %0(s32)
349    $rax = COPY %1(s64)
350    RET 0, implicit $rax
351
352...
353
354