1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=X64
3
4; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/bmi-builtins.c
5
6;
7; AMD Intrinsics
8;
9
10define i64 @test__andn_u64(i64 %a0, i64 %a1) {
11; X64-LABEL: test__andn_u64:
12; X64:       # %bb.0:
13; X64-NEXT:    movq %rdi, %rax
14; X64-NEXT:    xorq $-1, %rax
15; X64-NEXT:    andq %rsi, %rax
16; X64-NEXT:    retq
17  %xor = xor i64 %a0, -1
18  %res = and i64 %xor, %a1
19  ret i64 %res
20}
21
22define i64 @test__bextr_u64(i64 %a0, i64 %a1) {
23; X64-LABEL: test__bextr_u64:
24; X64:       # %bb.0:
25; X64-NEXT:    bextrq %rsi, %rdi, %rax
26; X64-NEXT:    retq
27  %res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %a1)
28  ret i64 %res
29}
30
31define i64 @test__blsi_u64(i64 %a0) {
32; X64-LABEL: test__blsi_u64:
33; X64:       # %bb.0:
34; X64-NEXT:    xorl %eax, %eax
35; X64-NEXT:    subq %rdi, %rax
36; X64-NEXT:    andq %rdi, %rax
37; X64-NEXT:    retq
38  %neg = sub i64 0, %a0
39  %res = and i64 %a0, %neg
40  ret i64 %res
41}
42
43define i64 @test__blsmsk_u64(i64 %a0) {
44; X64-LABEL: test__blsmsk_u64:
45; X64:       # %bb.0:
46; X64-NEXT:    leaq -1(%rdi), %rax
47; X64-NEXT:    xorq %rdi, %rax
48; X64-NEXT:    retq
49  %dec = sub i64 %a0, 1
50  %res = xor i64 %a0, %dec
51  ret i64 %res
52}
53
54define i64 @test__blsr_u64(i64 %a0) {
55; X64-LABEL: test__blsr_u64:
56; X64:       # %bb.0:
57; X64-NEXT:    leaq -1(%rdi), %rax
58; X64-NEXT:    andq %rdi, %rax
59; X64-NEXT:    retq
60  %dec = sub i64 %a0, 1
61  %res = and i64 %a0, %dec
62  ret i64 %res
63}
64
65define i64 @test__tzcnt_u64(i64 %a0) {
66; X64-LABEL: test__tzcnt_u64:
67; X64:       # %bb.0:
68; X64-NEXT:    tzcntq %rdi, %rax
69; X64-NEXT:    retq
70  %cmp = icmp ne i64 %a0, 0
71  %cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 false)
72  ret i64 %cttz
73}
74
75;
76; Intel intrinsics
77;
78
79define i64 @test_andn_u64(i64 %a0, i64 %a1) {
80; X64-LABEL: test_andn_u64:
81; X64:       # %bb.0:
82; X64-NEXT:    movq %rdi, %rax
83; X64-NEXT:    xorq $-1, %rax
84; X64-NEXT:    andq %rsi, %rax
85; X64-NEXT:    retq
86  %xor = xor i64 %a0, -1
87  %res = and i64 %xor, %a1
88  ret i64 %res
89}
90
91define i64 @test_bextr_u64(i64 %a0, i32 %a1, i32 %a2) {
92; X64-LABEL: test_bextr_u64:
93; X64:       # %bb.0:
94; X64-NEXT:    andl $255, %esi
95; X64-NEXT:    andl $255, %edx
96; X64-NEXT:    shll $8, %edx
97; X64-NEXT:    orl %esi, %edx
98; X64-NEXT:    movl %edx, %eax
99; X64-NEXT:    bextrq %rax, %rdi, %rax
100; X64-NEXT:    retq
101  %and1 = and i32 %a1, 255
102  %and2 = and i32 %a2, 255
103  %shl = shl i32 %and2, 8
104  %or = or i32 %and1, %shl
105  %zext = zext i32 %or to i64
106  %res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %zext)
107  ret i64 %res
108}
109
110define i64 @test_blsi_u64(i64 %a0) {
111; X64-LABEL: test_blsi_u64:
112; X64:       # %bb.0:
113; X64-NEXT:    xorl %eax, %eax
114; X64-NEXT:    subq %rdi, %rax
115; X64-NEXT:    andq %rdi, %rax
116; X64-NEXT:    retq
117  %neg = sub i64 0, %a0
118  %res = and i64 %a0, %neg
119  ret i64 %res
120}
121
122define i64 @test_blsmsk_u64(i64 %a0) {
123; X64-LABEL: test_blsmsk_u64:
124; X64:       # %bb.0:
125; X64-NEXT:    leaq -1(%rdi), %rax
126; X64-NEXT:    xorq %rdi, %rax
127; X64-NEXT:    retq
128  %dec = sub i64 %a0, 1
129  %res = xor i64 %a0, %dec
130  ret i64 %res
131}
132
133define i64 @test_blsr_u64(i64 %a0) {
134; X64-LABEL: test_blsr_u64:
135; X64:       # %bb.0:
136; X64-NEXT:    leaq -1(%rdi), %rax
137; X64-NEXT:    andq %rdi, %rax
138; X64-NEXT:    retq
139  %dec = sub i64 %a0, 1
140  %res = and i64 %a0, %dec
141  ret i64 %res
142}
143
144define i64 @test_tzcnt_u64(i64 %a0) {
145; X64-LABEL: test_tzcnt_u64:
146; X64:       # %bb.0:
147; X64-NEXT:    tzcntq %rdi, %rax
148; X64-NEXT:    retq
149  %cmp = icmp ne i64 %a0, 0
150  %cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 false)
151  ret i64 %cttz
152}
153
154declare i64 @llvm.cttz.i64(i64, i1)
155declare i64 @llvm.x86.bmi.bextr.64(i64, i64)
156