1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3; PR4572
4
5; Don't coalesce with %esp if it would end up putting %esp in
6; the index position of an address, because that can't be
7; encoded on x86. It would actually be slightly better to
8; swap the address operands though, since there's no scale.
9
10target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
11target triple = "i386-pc-mingw32"
12	%"struct.std::valarray<unsigned int>" = type { i32, i32* }
13
14define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, %"struct.std::valarray<unsigned int>"* nocapture %__l, %"struct.std::valarray<unsigned int>"* nocapture %__s, %"struct.std::valarray<unsigned int>"* nocapture %__i) nounwind {
15; CHECK-LABEL: _ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_:
16; CHECK:       # %bb.0: # %entry
17; CHECK-NEXT:    pushl %ebp
18; CHECK-NEXT:    movl %esp, %ebp
19; CHECK-NEXT:    movl %esp, %eax
20; CHECK-NEXT:    xorl %ecx, %ecx
21; CHECK-NEXT:    testb %cl, %cl
22; CHECK-NEXT:    je .LBB0_1
23; CHECK-NEXT:  # %bb.5: # %return
24; CHECK-NEXT:    movl %ebp, %esp
25; CHECK-NEXT:    popl %ebp
26; CHECK-NEXT:    retl
27; CHECK-NEXT:  .LBB0_1: # %bb4.preheader
28; CHECK-NEXT:    xorl %edx, %edx
29; CHECK-NEXT:    jmp .LBB0_2
30; CHECK-NEXT:    .p2align 4, 0x90
31; CHECK-NEXT:  .LBB0_4: # %bb7.backedge
32; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
33; CHECK-NEXT:    addl $-4, %edx
34; CHECK-NEXT:  .LBB0_2: # %bb4
35; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
36; CHECK-NEXT:    testb %cl, %cl
37; CHECK-NEXT:    jne .LBB0_4
38; CHECK-NEXT:  # %bb.3: # %bb5
39; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
40; CHECK-NEXT:    movl $0, (%eax,%edx)
41; CHECK-NEXT:    jmp .LBB0_4
42entry:
43	%0 = alloca i32, i32 undef, align 4		; <i32*> [#uses=1]
44	br i1 undef, label %return, label %bb4
45
46bb4:		; preds = %bb7.backedge, %entry
47	%indvar = phi i32 [ %indvar.next, %bb7.backedge ], [ 0, %entry ]		; <i32> [#uses=2]
48	%scevgep24.sum = sub i32 undef, %indvar		; <i32> [#uses=2]
49	%scevgep25 = getelementptr i32, i32* %0, i32 %scevgep24.sum		; <i32*> [#uses=1]
50	%scevgep27 = getelementptr i32, i32* undef, i32 %scevgep24.sum		; <i32*> [#uses=1]
51	%1 = load i32, i32* %scevgep27, align 4		; <i32> [#uses=0]
52	br i1 undef, label %bb7.backedge, label %bb5
53
54bb5:		; preds = %bb4
55	store i32 0, i32* %scevgep25, align 4
56	br label %bb7.backedge
57
58bb7.backedge:		; preds = %bb5, %bb4
59	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
60	br label %bb4
61
62return:		; preds = %entry
63	ret void
64}
65