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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,SSE
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=CHECK,AVX
4; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX
5
6define i64 @testmsxs(float %x) {
7; SSE-LABEL: testmsxs:
8; SSE:       # %bb.0: # %entry
9; SSE-NEXT:    cvtss2si %xmm0, %rax
10; SSE-NEXT:    retq
11;
12; AVX-LABEL: testmsxs:
13; AVX:       # %bb.0: # %entry
14; AVX-NEXT:    vcvtss2si %xmm0, %rax
15; AVX-NEXT:    retq
16entry:
17  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
18  ret i64 %0
19}
20
21define i64 @testmsxd(double %x) {
22; SSE-LABEL: testmsxd:
23; SSE:       # %bb.0: # %entry
24; SSE-NEXT:    cvtsd2si %xmm0, %rax
25; SSE-NEXT:    retq
26;
27; AVX-LABEL: testmsxd:
28; AVX:       # %bb.0: # %entry
29; AVX-NEXT:    vcvtsd2si %xmm0, %rax
30; AVX-NEXT:    retq
31entry:
32  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
33  ret i64 %0
34}
35
36define i64 @testmsll(x86_fp80 %x) {
37; CHECK-LABEL: testmsll:
38; CHECK:       # %bb.0: # %entry
39; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
40; CHECK-NEXT:    fistpll -{{[0-9]+}}(%rsp)
41; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
42; CHECK-NEXT:    retq
43entry:
44  %0 = tail call i64 @llvm.lrint.i64.f80(x86_fp80 %x)
45  ret i64 %0
46}
47
48declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
49declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
50declare i64 @llvm.lrint.i64.f80(x86_fp80) nounwind readnone
51