1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s
3
4%SA = type <{ %union.anon, i32, [4 x i8], i8*, i8*, i8*, i32, [4 x i8] }>
5%union.anon = type { <1 x i64> }
6
7; Check that extra movd (copy) instructions aren't generated.
8
9define i32 @test(%SA* %pSA, i16* %A, i32 %B, i32 %C, i32 %D, i8* %E) {
10; CHECK-LABEL: test:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    pshufw $238, (%rdi), %mm0 # mm0 = mem[2,3,2,3]
13; CHECK-NEXT:    movd %mm0, %eax
14; CHECK-NEXT:    testl %eax, %eax
15; CHECK-NEXT:    je .LBB0_1
16; CHECK-NEXT:  # %bb.2: # %if.B
17; CHECK-NEXT:    pshufw $238, %mm0, %mm0 # mm0 = mm0[2,3,2,3]
18; CHECK-NEXT:    movq %mm0, %rax
19; CHECK-NEXT:    jmp .LBB0_3
20; CHECK-NEXT:  .LBB0_1: # %if.A
21; CHECK-NEXT:    movd %edx, %mm1
22; CHECK-NEXT:    psllq %mm1, %mm0
23; CHECK-NEXT:    movq %mm0, %rax
24; CHECK-NEXT:    testq %rax, %rax
25; CHECK-NEXT:    jne .LBB0_4
26; CHECK-NEXT:  .LBB0_3: # %if.C
27; CHECK-NEXT:    testl %eax, %eax
28; CHECK-NEXT:    je .LBB0_1
29; CHECK-NEXT:  .LBB0_4: # %merge
30; CHECK-NEXT:    pshufw $238, %mm0, %mm0 # mm0 = mm0[2,3,2,3]
31; CHECK-NEXT:    movd %mm0, %eax
32; CHECK-NEXT:    retq
33entry:
34  %shl = shl i32 1, %B
35  %shl1 = shl i32 %C, %B
36  %shl2 = shl i32 1, %D
37  %v = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 0, i32 0
38  %v0 = load <1 x i64>, <1 x i64>* %v, align 8
39  %SA0 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 1
40  %v1 = load i32, i32* %SA0, align 4
41  %SA1 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 3
42  %v2 = load i8*, i8** %SA1, align 8
43  %SA2 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 4
44  %v3 = load i8*, i8** %SA2, align 8
45  %v4 = bitcast <1 x i64> %v0 to <4 x i16>
46  %v5 = bitcast <4 x i16> %v4 to x86_mmx
47  %v6 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v5, i8 -18)
48  %v7 = bitcast x86_mmx %v6 to <4 x i16>
49  %v8 = bitcast <4 x i16> %v7 to <1 x i64>
50  %v9 = extractelement <1 x i64> %v8, i32 0
51  %v10 = bitcast i64 %v9 to <2 x i32>
52  %v11 = extractelement <2 x i32> %v10, i32 0
53  %cmp = icmp eq i32 %v11, 0
54  br i1 %cmp, label %if.A, label %if.B
55
56if.A:
57  %pa = phi <1 x i64> [ %v8, %entry ], [ %vx, %if.C ]
58  %v17 = extractelement <1 x i64> %pa, i32 0
59  %v18 = bitcast i64 %v17 to x86_mmx
60  %v19 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %v18, i32 %B) #2
61  %v20 = bitcast x86_mmx %v19 to i64
62  %v21 = insertelement <1 x i64> undef, i64 %v20, i32 0
63  %cmp3 = icmp eq i64 %v20, 0
64  br i1 %cmp3, label %if.C, label %merge
65
66if.B:
67  %v34 = bitcast <1 x i64> %v8 to <4 x i16>
68  %v35 = bitcast <4 x i16> %v34 to x86_mmx
69  %v36 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v35, i8 -18)
70  %v37 = bitcast x86_mmx %v36 to <4 x i16>
71  %v38 = bitcast <4 x i16> %v37 to <1 x i64>
72  br label %if.C
73
74if.C:
75  %vx = phi <1 x i64> [ %v21, %if.A ], [ %v38, %if.B ]
76  %cvt = bitcast <1 x i64> %vx to <2 x i32>
77  %ex = extractelement <2 x i32> %cvt, i32 0
78  %cmp2 = icmp eq i32 %ex, 0
79  br i1 %cmp2, label %if.A, label %merge
80
81merge:
82  %vy = phi <1 x i64> [ %v21, %if.A ], [ %vx, %if.C ]
83  %v130 = bitcast <1 x i64> %vy to <4 x i16>
84  %v131 = bitcast <4 x i16> %v130 to x86_mmx
85  %v132 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v131, i8 -18)
86  %v133 = bitcast x86_mmx %v132 to <4 x i16>
87  %v134 = bitcast <4 x i16> %v133 to <1 x i64>
88  %v135 = extractelement <1 x i64> %v134, i32 0
89  %v136 = bitcast i64 %v135 to <2 x i32>
90  %v137 = extractelement <2 x i32> %v136, i32 0
91  ret i32 %v137
92}
93
94
95declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
96declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
97