1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2     | FileCheck %s --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1   | FileCheck %s --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx      | FileCheck %s --check-prefix=AVX
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2     | FileCheck %s --check-prefix=AVX
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f  | FileCheck %s --check-prefix=AVX
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw | FileCheck %s --check-prefix=AVX
8
9declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
10
11define i1 @parseHeaders(i64 * %ptr) nounwind {
12; SSE2-LABEL: parseHeaders:
13; SSE2:       # %bb.0:
14; SSE2-NEXT:    movdqu (%rdi), %xmm0
15; SSE2-NEXT:    pxor %xmm1, %xmm1
16; SSE2-NEXT:    pcmpeqb %xmm0, %xmm1
17; SSE2-NEXT:    pmovmskb %xmm1, %eax
18; SSE2-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
19; SSE2-NEXT:    sete %al
20; SSE2-NEXT:    retq
21;
22; SSE41-LABEL: parseHeaders:
23; SSE41:       # %bb.0:
24; SSE41-NEXT:    movdqu (%rdi), %xmm0
25; SSE41-NEXT:    ptest %xmm0, %xmm0
26; SSE41-NEXT:    sete %al
27; SSE41-NEXT:    retq
28;
29; AVX-LABEL: parseHeaders:
30; AVX:       # %bb.0:
31; AVX-NEXT:    vmovdqu (%rdi), %xmm0
32; AVX-NEXT:    vptest %xmm0, %xmm0
33; AVX-NEXT:    sete %al
34; AVX-NEXT:    retq
35  %vptr = bitcast i64 * %ptr to <2 x i64> *
36  %vload = load <2 x i64>, <2 x i64> * %vptr, align 8
37  %vreduce = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %vload)
38  %vcheck = icmp eq i64 %vreduce, 0
39  ret i1 %vcheck
40}
41
42define i1 @parseHeaders2_scalar_or(i64 * %ptr) nounwind {
43; SSE2-LABEL: parseHeaders2_scalar_or:
44; SSE2:       # %bb.0:
45; SSE2-NEXT:    movdqu (%rdi), %xmm0
46; SSE2-NEXT:    pxor %xmm1, %xmm1
47; SSE2-NEXT:    pcmpeqb %xmm0, %xmm1
48; SSE2-NEXT:    pmovmskb %xmm1, %eax
49; SSE2-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
50; SSE2-NEXT:    sete %al
51; SSE2-NEXT:    retq
52;
53; SSE41-LABEL: parseHeaders2_scalar_or:
54; SSE41:       # %bb.0:
55; SSE41-NEXT:    movdqu (%rdi), %xmm0
56; SSE41-NEXT:    ptest %xmm0, %xmm0
57; SSE41-NEXT:    sete %al
58; SSE41-NEXT:    retq
59;
60; AVX-LABEL: parseHeaders2_scalar_or:
61; AVX:       # %bb.0:
62; AVX-NEXT:    vmovdqu (%rdi), %xmm0
63; AVX-NEXT:    vptest %xmm0, %xmm0
64; AVX-NEXT:    sete %al
65; AVX-NEXT:    retq
66  %vptr = bitcast i64 * %ptr to <2 x i64> *
67  %vload = load <2 x i64>, <2 x i64> * %vptr, align 8
68  %v1 = extractelement <2 x i64> %vload, i32 0
69  %v2 = extractelement <2 x i64> %vload, i32 1
70  %vreduce = or i64 %v1, %v2
71  %vcheck = icmp eq i64 %vreduce, 0
72  ret i1 %vcheck
73}
74
75define i1 @parseHeaders2_scalar_and(i64 * %ptr) nounwind {
76; SSE2-LABEL: parseHeaders2_scalar_and:
77; SSE2:       # %bb.0:
78; SSE2-NEXT:    movdqu (%rdi), %xmm0
79; SSE2-NEXT:    movq %xmm0, %rax
80; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
81; SSE2-NEXT:    movq %xmm0, %rcx
82; SSE2-NEXT:    testq %rcx, %rax
83; SSE2-NEXT:    sete %al
84; SSE2-NEXT:    retq
85;
86; SSE41-LABEL: parseHeaders2_scalar_and:
87; SSE41:       # %bb.0:
88; SSE41-NEXT:    movdqu (%rdi), %xmm0
89; SSE41-NEXT:    movq %xmm0, %rax
90; SSE41-NEXT:    pextrq $1, %xmm0, %rcx
91; SSE41-NEXT:    testq %rcx, %rax
92; SSE41-NEXT:    sete %al
93; SSE41-NEXT:    retq
94;
95; AVX-LABEL: parseHeaders2_scalar_and:
96; AVX:       # %bb.0:
97; AVX-NEXT:    vmovdqu (%rdi), %xmm0
98; AVX-NEXT:    vmovq %xmm0, %rax
99; AVX-NEXT:    vpextrq $1, %xmm0, %rcx
100; AVX-NEXT:    testq %rcx, %rax
101; AVX-NEXT:    sete %al
102; AVX-NEXT:    retq
103  %vptr = bitcast i64 * %ptr to <2 x i64> *
104  %vload = load <2 x i64>, <2 x i64> * %vptr, align 8
105  %v1 = extractelement <2 x i64> %vload, i32 0
106  %v2 = extractelement <2 x i64> %vload, i32 1
107  %vreduce = and i64 %v1, %v2
108  %vcheck = icmp eq i64 %vreduce, 0
109  ret i1 %vcheck
110}
111