1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
4
5; Only bottom 16 bits are set - upper 48 bits are zero.
6define <2 x i64> @combine_psadbw_shift(<16 x i8> %0, <16 x i8> %1) {
7; CHECK-LABEL: combine_psadbw_shift:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    xorps %xmm0, %xmm0
10; CHECK-NEXT:    ret{{[l|q]}}
11  %3 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %0, <16 x i8> %1)
12  %4 = lshr <2 x i64> %3, <i64 48, i64 48>
13  ret <2 x i64> %4
14}
15
16; Propagate the demanded result elements to the 8 aliasing source elements.
17define i64 @combine_psadbw_demandedelt(<16 x i8> %0, <16 x i8> %1) {
18; X86-LABEL: combine_psadbw_demandedelt:
19; X86:       # %bb.0:
20; X86-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
21; X86-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,3,2]
22; X86-NEXT:    psadbw %xmm0, %xmm1
23; X86-NEXT:    movd %xmm1, %eax
24; X86-NEXT:    xorl %edx, %edx
25; X86-NEXT:    retl
26;
27; X64-LABEL: combine_psadbw_demandedelt:
28; X64:       # %bb.0:
29; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
30; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,3,2]
31; X64-NEXT:    psadbw %xmm0, %xmm1
32; X64-NEXT:    movq %xmm1, %rax
33; X64-NEXT:    retq
34  %3 = shufflevector <16 x i8> %0, <16 x i8> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
35  %4 = shufflevector <16 x i8> %1, <16 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
36  %5 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %3, <16 x i8> %4)
37  %6 = extractelement <2 x i64> %5, i32 0
38  ret i64 %6
39}
40
41declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>)
42
43