1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
3
4; If positive...
5
6define i32 @zext_ifpos(i32 %x) {
7; CHECK-LABEL: zext_ifpos:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    movl %edi, %eax
10; CHECK-NEXT:    notl %eax
11; CHECK-NEXT:    shrl $31, %eax
12; CHECK-NEXT:    retq
13  %c = icmp sgt i32 %x, -1
14  %e = zext i1 %c to i32
15  ret i32 %e
16}
17
18define i32 @add_zext_ifpos(i32 %x) {
19; CHECK-LABEL: add_zext_ifpos:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
22; CHECK-NEXT:    sarl $31, %edi
23; CHECK-NEXT:    leal 42(%rdi), %eax
24; CHECK-NEXT:    retq
25  %c = icmp sgt i32 %x, -1
26  %e = zext i1 %c to i32
27  %r = add i32 %e, 41
28  ret i32 %r
29}
30
31define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
32; CHECK-LABEL: add_zext_ifpos_vec_splat:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
35; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
36; CHECK-NEXT:    movdqa {{.*#+}} xmm1 = [42,42,42,42]
37; CHECK-NEXT:    psubd %xmm0, %xmm1
38; CHECK-NEXT:    movdqa %xmm1, %xmm0
39; CHECK-NEXT:    retq
40  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
41  %e = zext <4 x i1> %c to <4 x i32>
42  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
43  ret <4 x i32> %r
44}
45
46define <4 x i32> @add_zext_ifpos_vec_nonsplat(<4 x i32> %x) {
47; CHECK-LABEL: add_zext_ifpos_vec_nonsplat:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
50; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
51; CHECK-NEXT:    movdqa {{.*#+}} xmm1 = [42,43,44,45]
52; CHECK-NEXT:    psubd %xmm0, %xmm1
53; CHECK-NEXT:    movdqa %xmm1, %xmm0
54; CHECK-NEXT:    retq
55  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
56  %e = zext <4 x i1> %c to <4 x i32>
57  %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
58  ret <4 x i32> %r
59}
60
61define i32 @sel_ifpos_tval_bigger(i32 %x) {
62; CHECK-LABEL: sel_ifpos_tval_bigger:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
65; CHECK-NEXT:    sarl $31, %edi
66; CHECK-NEXT:    leal 42(%rdi), %eax
67; CHECK-NEXT:    retq
68  %c = icmp sgt i32 %x, -1
69  %r = select i1 %c, i32 42, i32 41
70  ret i32 %r
71}
72
73define i32 @sext_ifpos(i32 %x) {
74; CHECK-LABEL: sext_ifpos:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    movl %edi, %eax
77; CHECK-NEXT:    notl %eax
78; CHECK-NEXT:    sarl $31, %eax
79; CHECK-NEXT:    retq
80  %c = icmp sgt i32 %x, -1
81  %e = sext i1 %c to i32
82  ret i32 %e
83}
84
85define i32 @add_sext_ifpos(i32 %x) {
86; CHECK-LABEL: add_sext_ifpos:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
89; CHECK-NEXT:    shrl $31, %edi
90; CHECK-NEXT:    leal 41(%rdi), %eax
91; CHECK-NEXT:    retq
92  %c = icmp sgt i32 %x, -1
93  %e = sext i1 %c to i32
94  %r = add i32 %e, 42
95  ret i32 %r
96}
97
98define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
99; CHECK-LABEL: add_sext_ifpos_vec_splat:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
102; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
103; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
104; CHECK-NEXT:    retq
105  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
106  %e = sext <4 x i1> %c to <4 x i32>
107  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
108  ret <4 x i32> %r
109}
110
111define <4 x i32> @add_sext_ifpos_vec_nonsplat(<4 x i32> %x) {
112; CHECK-LABEL: add_sext_ifpos_vec_nonsplat:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    pcmpeqd %xmm1, %xmm1
115; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
116; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
117; CHECK-NEXT:    retq
118  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
119  %e = sext <4 x i1> %c to <4 x i32>
120  %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
121  ret <4 x i32> %r
122}
123
124define i32 @sel_ifpos_fval_bigger(i32 %x) {
125; CHECK-LABEL: sel_ifpos_fval_bigger:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
128; CHECK-NEXT:    shrl $31, %edi
129; CHECK-NEXT:    leal 41(%rdi), %eax
130; CHECK-NEXT:    retq
131  %c = icmp sgt i32 %x, -1
132  %r = select i1 %c, i32 41, i32 42
133  ret i32 %r
134}
135
136; If negative...
137
138define i32 @zext_ifneg(i32 %x) {
139; CHECK-LABEL: zext_ifneg:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    movl %edi, %eax
142; CHECK-NEXT:    shrl $31, %eax
143; CHECK-NEXT:    retq
144  %c = icmp slt i32 %x, 0
145  %r = zext i1 %c to i32
146  ret i32 %r
147}
148
149define i32 @add_zext_ifneg(i32 %x) {
150; CHECK-LABEL: add_zext_ifneg:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
153; CHECK-NEXT:    shrl $31, %edi
154; CHECK-NEXT:    leal 41(%rdi), %eax
155; CHECK-NEXT:    retq
156  %c = icmp slt i32 %x, 0
157  %e = zext i1 %c to i32
158  %r = add i32 %e, 41
159  ret i32 %r
160}
161
162define i32 @sel_ifneg_tval_bigger(i32 %x) {
163; CHECK-LABEL: sel_ifneg_tval_bigger:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
166; CHECK-NEXT:    shrl $31, %edi
167; CHECK-NEXT:    leal 41(%rdi), %eax
168; CHECK-NEXT:    retq
169  %c = icmp slt i32 %x, 0
170  %r = select i1 %c, i32 42, i32 41
171  ret i32 %r
172}
173
174define i32 @sext_ifneg(i32 %x) {
175; CHECK-LABEL: sext_ifneg:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    movl %edi, %eax
178; CHECK-NEXT:    sarl $31, %eax
179; CHECK-NEXT:    retq
180  %c = icmp slt i32 %x, 0
181  %r = sext i1 %c to i32
182  ret i32 %r
183}
184
185define i32 @add_sext_ifneg(i32 %x) {
186; CHECK-LABEL: add_sext_ifneg:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
189; CHECK-NEXT:    sarl $31, %edi
190; CHECK-NEXT:    leal 42(%rdi), %eax
191; CHECK-NEXT:    retq
192  %c = icmp slt i32 %x, 0
193  %e = sext i1 %c to i32
194  %r = add i32 %e, 42
195  ret i32 %r
196}
197
198define i32 @sel_ifneg_fval_bigger(i32 %x) {
199; CHECK-LABEL: sel_ifneg_fval_bigger:
200; CHECK:       # %bb.0:
201; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
202; CHECK-NEXT:    sarl $31, %edi
203; CHECK-NEXT:    leal 42(%rdi), %eax
204; CHECK-NEXT:    retq
205  %c = icmp slt i32 %x, 0
206  %r = select i1 %c, i32 41, i32 42
207  ret i32 %r
208}
209
210define i32 @add_lshr_not(i32 %x) {
211; CHECK-LABEL: add_lshr_not:
212; CHECK:       # %bb.0:
213; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
214; CHECK-NEXT:    sarl $31, %edi
215; CHECK-NEXT:    leal 42(%rdi), %eax
216; CHECK-NEXT:    retq
217  %not = xor i32 %x, -1
218  %sh = lshr i32 %not, 31
219  %r = add i32 %sh, 41
220  ret i32 %r
221}
222
223define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
224; CHECK-LABEL: add_lshr_not_vec_splat:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    psrad $31, %xmm0
227; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
228; CHECK-NEXT:    retq
229  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
230  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
231  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
232  ret <4 x i32> %r
233}
234
235define <4 x i32> @add_lshr_not_vec_nonsplat(<4 x i32> %x) {
236; CHECK-LABEL: add_lshr_not_vec_nonsplat:
237; CHECK:       # %bb.0:
238; CHECK-NEXT:    psrad $31, %xmm0
239; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
240; CHECK-NEXT:    retq
241  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
242  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
243  %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
244  ret <4 x i32> %r
245}
246
247define i32 @sub_lshr_not(i32 %x) {
248; CHECK-LABEL: sub_lshr_not:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
251; CHECK-NEXT:    shrl $31, %edi
252; CHECK-NEXT:    leal 42(%rdi), %eax
253; CHECK-NEXT:    retq
254  %not = xor i32 %x, -1
255  %sh = lshr i32 %not, 31
256  %r = sub i32 43, %sh
257  ret i32 %r
258}
259
260define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
261; CHECK-LABEL: sub_lshr_not_vec_splat:
262; CHECK:       # %bb.0:
263; CHECK-NEXT:    psrld $31, %xmm0
264; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
265; CHECK-NEXT:    retq
266  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
267  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
268  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
269  ret <4 x i32> %r
270}
271
272define <4 x i32> @sub_lshr_not_vec_nonsplat(<4 x i32> %x) {
273; CHECK-LABEL: sub_lshr_not_vec_nonsplat:
274; CHECK:       # %bb.0:
275; CHECK-NEXT:    psrld $31, %xmm0
276; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
277; CHECK-NEXT:    retq
278  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
279  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
280  %r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %e
281  ret <4 x i32> %r
282}
283
284define i32 @sub_lshr(i32 %x, i32 %y) {
285; CHECK-LABEL: sub_lshr:
286; CHECK:       # %bb.0:
287; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
288; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
289; CHECK-NEXT:    sarl $31, %edi
290; CHECK-NEXT:    leal (%rdi,%rsi), %eax
291; CHECK-NEXT:    retq
292  %sh = lshr i32 %x, 31
293  %r = sub i32 %y, %sh
294  ret i32 %r
295}
296
297define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
298; CHECK-LABEL: sub_lshr_vec:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    psrad $31, %xmm0
301; CHECK-NEXT:    paddd %xmm1, %xmm0
302; CHECK-NEXT:    retq
303  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
304  %r = sub <4 x i32> %y, %sh
305  ret <4 x i32> %r
306}
307
308define i32 @sub_const_op_lshr(i32 %x) {
309; CHECK-LABEL: sub_const_op_lshr:
310; CHECK:       # %bb.0:
311; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
312; CHECK-NEXT:    sarl $31, %edi
313; CHECK-NEXT:    leal 43(%rdi), %eax
314; CHECK-NEXT:    retq
315  %sh = lshr i32 %x, 31
316  %r = sub i32 43, %sh
317  ret i32 %r
318}
319
320define <4 x i32> @sub_const_op_lshr_vec_splat(<4 x i32> %x) {
321; CHECK-LABEL: sub_const_op_lshr_vec_splat:
322; CHECK:       # %bb.0:
323; CHECK-NEXT:    psrad $31, %xmm0
324; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
325; CHECK-NEXT:    retq
326  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
327  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
328  ret <4 x i32> %r
329}
330
331define <4 x i32> @sub_const_op_lshr_vec_nonsplat(<4 x i32> %x) {
332; CHECK-LABEL: sub_const_op_lshr_vec_nonsplat:
333; CHECK:       # %bb.0:
334; CHECK-NEXT:    psrad $31, %xmm0
335; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
336; CHECK-NEXT:    retq
337  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
338  %r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %sh
339  ret <4 x i32> %r
340}
341
342