1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
6
7define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
8; SSE2-LABEL: test1:
9; SSE2:       # %bb.0:
10; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
11; SSE2-NEXT:    retq
12;
13; SSE41-LABEL: test1:
14; SSE41:       # %bb.0:
15; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
16; SSE41-NEXT:    retq
17;
18; AVX-LABEL: test1:
19; AVX:       # %bb.0:
20; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
21; AVX-NEXT:    retq
22  %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B
23  ret <4 x i32> %select
24}
25
26define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
27; SSE2-LABEL: test2:
28; SSE2:       # %bb.0:
29; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
30; SSE2-NEXT:    retq
31;
32; SSE41-LABEL: test2:
33; SSE41:       # %bb.0:
34; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
35; SSE41-NEXT:    retq
36;
37; AVX-LABEL: test2:
38; AVX:       # %bb.0:
39; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
40; AVX-NEXT:    retq
41  %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x i32> %A, <4 x i32> %B
42  ret <4 x i32> %select
43}
44
45define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
46; SSE2-LABEL: test3:
47; SSE2:       # %bb.0:
48; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
49; SSE2-NEXT:    retq
50;
51; SSE41-LABEL: test3:
52; SSE41:       # %bb.0:
53; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
54; SSE41-NEXT:    retq
55;
56; AVX-LABEL: test3:
57; AVX:       # %bb.0:
58; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
59; AVX-NEXT:    retq
60  %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x float> %A, <4 x float> %B
61  ret <4 x float> %select
62}
63
64define <4 x float> @test4(<4 x float> %A, <4 x float> %B) {
65; SSE2-LABEL: test4:
66; SSE2:       # %bb.0:
67; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
68; SSE2-NEXT:    retq
69;
70; SSE41-LABEL: test4:
71; SSE41:       # %bb.0:
72; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
73; SSE41-NEXT:    retq
74;
75; AVX-LABEL: test4:
76; AVX:       # %bb.0:
77; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
78; AVX-NEXT:    retq
79  %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x float> %A, <4 x float> %B
80  ret <4 x float> %select
81}
82