1; RUN: opt < %s -asan -enable-new-pm=0 -S -o %t.ll
2; RUN: opt < %s -passes='asan-function-pipeline' -S -o %t.ll
3; RUN: FileCheck %s < %t.ll
4; RUN: llc < %t.ll | FileCheck %s --check-prefix=ASM
5
6target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32"
7target triple = "i386-pc-windows-msvc"
8
9define void @MyCPUID(i32 %fxn, i32* %out) sanitize_address {
10  %fxn.ptr = alloca i32
11  %a.ptr = alloca i32
12  %b.ptr = alloca i32
13  %c.ptr = alloca i32
14  %d.ptr = alloca i32
15  store i32 %fxn, i32* %fxn.ptr
16  call void asm sideeffect inteldialect "xchg ebx, esi\0A\09mov eax, dword ptr $4\0A\09cpuid\0A\09mov dword ptr $0, eax\0A\09mov dword ptr $1, ebx\0A\09mov dword ptr $2, ecx\0A\09mov dword ptr $3, edx\0A\09xchg ebx, esi", "=*m,=*m,=*m,=*m,*m,~{eax},~{ebx},~{ecx},~{edx},~{esi},~{dirflag},~{fpsr},~{flags}"(i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr, i32* %fxn.ptr)
17
18  %a = load i32, i32* %a.ptr
19  %a.out = getelementptr inbounds i32, i32* %out, i32 0
20  store i32 %a, i32* %a.out
21
22  %b = load i32, i32* %b.ptr
23  %b.out = getelementptr inbounds i32, i32* %out, i32 1
24  store i32 %b, i32* %b.out
25
26  %c = load i32, i32* %c.ptr
27  %c.out = getelementptr inbounds i32, i32* %out, i32 2
28  store i32 %c, i32* %c.out
29
30  %d = load i32, i32* %d.ptr
31  %d.out = getelementptr inbounds i32, i32* %out, i32 3
32  store i32 %d, i32* %d.out
33
34  ret void
35}
36
37; We used to introduce stack mallocs for UAR detection, but that makes LLVM run
38; out of registers on 32-bit platforms. Therefore, we don't do stack malloc on
39; such functions.
40
41; CHECK-LABEL: define void @MyCPUID(i32 %fxn, i32* %out)
42; CHECK: %MyAlloca = alloca [96 x i8], align 32
43; CHECK-NOT: call {{.*}} @__asan_stack_malloc
44
45; The code generator should recognize that all operands are just stack memory.
46; This is important with MS inline asm where operand lists are implicit and all
47; local variables can be referenced freely.
48
49; ASM-LABEL: MyCPUID:
50; ASM:      cpuid
51; ASM-NEXT: movl    %eax, {{[0-9]+}}(%esp)
52; ASM-NEXT: movl    %ebx, {{[0-9]+}}(%esp)
53; ASM-NEXT: movl    %ecx, {{[0-9]+}}(%esp)
54; ASM-NEXT: movl    %edx, {{[0-9]+}}(%esp)
55