1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
2
3fmaxv b0, p7, z31.b
4// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
5// CHECK-NEXT: fmaxv b0, p7, z31.b
6// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
7
8
9// ------------------------------------------------------------------------- //
10// Invalid predicate operand
11
12fmaxv h0, p8, z31.h
13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
14// CHECK-NEXT: fmaxv h0, p8, z31.h
15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16
17fmaxv h0, p7.b, z31.h
18// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
19// CHECK-NEXT: fmaxv h0, p7.b, z31.h
20// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21
22fmaxv h0, p7.q, z31.h
23// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
24// CHECK-NEXT: fmaxv h0, p7.q, z31.h
25// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26
27
28// ------------------------------------------------------------------------- //
29// Result must be a valid FP register.
30
31fmaxv v0, p7, z31.h
32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
33// CHECK-NEXT: fmaxv v0, p7, z31.h
34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35
36// --------------------------------------------------------------------------//
37// Negative tests for instructions that are incompatible with movprfx
38
39movprfx z31.d, p7/z, z6.d
40fmaxv d0, p7, z31.d
41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
42// CHECK-NEXT: fmaxv d0, p7, z31.d
43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44
45movprfx z31, z6
46fmaxv d0, p7, z31.d
47// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
48// CHECK-NEXT: fmaxv d0, p7, z31.d
49// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
50