1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
2
3
4// --------------------------------------------------------------------------//
5// Immediate out of lower bound [-32, 28].
6
7st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-36, MUL VL]
8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
9// CHECK-NEXT: st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-36, MUL VL]
10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11
12st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #32, MUL VL]
13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
14// CHECK-NEXT: st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #32, MUL VL]
15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16
17
18// --------------------------------------------------------------------------//
19// Immediate not a multiple of four.
20
21st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-7, MUL VL]
22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
23// CHECK-NEXT: st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-7, MUL VL]
24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25
26st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL]
27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
28// CHECK-NEXT: st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL]
29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30
31
32// --------------------------------------------------------------------------//
33// Invalid scalar + scalar addressing modes
34
35st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0]
36// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
37// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0]
38// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
39
40st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr]
41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
42// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr]
43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44
45st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2]
46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
47// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2]
48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
49
50st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0]
51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
52// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0]
53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
54
55st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw]
56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
57// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw]
58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
59
60
61// --------------------------------------------------------------------------//
62// Invalid predicate
63
64st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
66// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
67// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
68
69st4h {z2.h, z3.h, z4.h, z5.h}, p7.b, [x15, #10, MUL VL]
70// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
71// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p7.b, [x15, #10, MUL VL]
72// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
73
74st4h {z2.h, z3.h, z4.h, z5.h}, p7.q, [x15, #10, MUL VL]
75// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
76// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p7.q, [x15, #10, MUL VL]
77// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
78
79
80// --------------------------------------------------------------------------//
81// Invalid vector list.
82
83st4h { }, p0, [x0]
84// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
85// CHECK-NEXT: st4h { }, p0, [x0]
86// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
87
88st4h { z0.h, z1.h, z2.h, z3.h, z4.h }, p0, [x0]
89// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
90// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h, z4.h }, p0, [x0]
91// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
92
93st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0]
94// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
95// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0]
96// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
97
98st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
99// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
100// CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
101// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
102
103st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
104// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
105// CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
106// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
107
108
109// --------------------------------------------------------------------------//
110// Negative tests for instructions that are incompatible with movprfx
111
112movprfx z21.h, p5/z, z28.h
113st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
114// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
115// CHECK-NEXT: st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
116// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
117
118movprfx z21, z28
119st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
120// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
121// CHECK-NEXT: st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
122// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
123