1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
2
3
4// --------------------------------------------------------------------------//
5// Invalid element width
6
7fcvtx    z0.b, p0/m, z0.b
8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
9// CHECK-NEXT: fcvtx    z0.b, p0/m, z0.b
10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11
12fcvtx    z0.h, p0/m, z0.h
13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
14// CHECK-NEXT: fcvtx    z0.h, p0/m, z0.h
15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16
17fcvtx    z0.s, p0/m, z0.s
18// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
19// CHECK-NEXT: fcvtx    z0.s, p0/m, z0.s
20// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21
22fcvtx    z0.d, p0/m, z0.d
23// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
24// CHECK-NEXT: fcvtx    z0.d, p0/m, z0.d
25// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26
27
28// --------------------------------------------------------------------------//
29// Invalid predicate operation
30
31fcvtx   z0.s, p0/z, z0.d
32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
33// CHECK-NEXT: fcvtx   z0.s, p0/z, z0.d
34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35
36
37// --------------------------------------------------------------------------//
38// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
39
40fcvtx    z0.s, p8/m, z0.d
41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
42// CHECK-NEXT: fcvtx    z0.s, p8/m, z0.d
43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44