1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
2
3
4// ------------------------------------------------------------------------- //
5// Invalid element width
6
7nbsl z0.b, z0.b, z1.s, z2.b
8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
9// CHECK-NEXT: nbsl z0.b, z0.b, z1.s, z2.b
10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11
12nbsl z0.h, z0.h, z1.h, z2.s
13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
14// CHECK-NEXT: nbsl z0.h, z0.h, z1.h, z2.s
15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16
17nbsl z0.d, z0.d, z1.s, z2.s
18// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
19// CHECK-NEXT: nbsl z0.d, z0.d, z1.s, z2.s
20// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21
22
23// --------------------------------------------------------------------------//
24// Source and Destination Registers must match
25
26nbsl z0.d, z1.d, z2.d, z3.d
27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
28// CHECK-NEXT: nbsl z0.d, z1.d, z2.d, z3.d
29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30
31
32// --------------------------------------------------------------------------//
33// Negative tests for instructions that are incompatible with movprfx
34
35movprfx z0.d, p0/z, z7.d
36nbsl z0.d, z0.d, z1.d, z2.d
37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
38// CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
40