1# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s 2> %t \
2# RUN:   | FileCheck --check-prefix=CHECK %s
3# RUN:     FileCheck --check-prefix=ERROR < %t %s
4
5# CHECK: vld20.8 {q0, q1}, [sp] @ encoding: [0x9d,0xfc,0x00,0x1e]
6vld20.8 {q0, q1}, [sp]
7
8# CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e]
9vld20.8 {q0, q1}, [r0]
10
11# CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e]
12vld20.8 {q0, q1}, [r0]!
13
14# CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e]
15vld20.8 {q0, q1}, [r11]
16
17# CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe]
18vld20.8 {q5, q6}, [r0]!
19
20# CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e]
21vld21.8 {q0, q1}, [r0]
22
23# CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
24vld21.8 {q3, q4}, [r0]!
25
26# CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e]
27vld20.16 {q0, q1}, [r0]
28
29# CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e]
30vld20.16 {q0, q1}, [r0]!
31
32# CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e]
33vld20.16 {q0, q1}, [r11]
34
35# CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe]
36vld20.16 {q5, q6}, [r0]!
37
38# CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e]
39vld21.16 {q0, q1}, [r0]
40
41# CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
42vld21.16 {q3, q4}, [r0]!
43
44# CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f]
45vld20.32 {q0, q1}, [r0]
46
47# CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f]
48vld20.32 {q0, q1}, [r0]!
49
50# CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f]
51vld20.32 {q0, q1}, [r11]
52
53# CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf]
54vld20.32 {q5, q6}, [r0]!
55
56# CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f]
57vld21.32 {q0, q1}, [r0]
58
59# CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
60vld21.32 {q3, q4}, [r0]!
61
62# CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e]
63vst20.8 {q0, q1}, [r0]
64
65# CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e]
66vst20.8 {q0, q1}, [r0]!
67
68# CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e]
69vst20.8 {q0, q1}, [r11]
70
71# CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe]
72vst20.8 {q5, q6}, [r0]!
73
74# CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e]
75vst21.8 {q0, q1}, [r0]
76
77# CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
78vst21.8 {q3, q4}, [r0]!
79
80# CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e]
81vst20.16 {q0, q1}, [r0]
82
83# CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e]
84vst20.16 {q0, q1}, [r0]!
85
86# CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e]
87vst20.16 {q0, q1}, [r11]
88
89# CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe]
90vst20.16 {q5, q6}, [r0]!
91
92# CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e]
93vst21.16 {q0, q1}, [r0]
94
95# CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
96vst21.16 {q3, q4}, [r0]!
97
98# CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f]
99vst20.32 {q0, q1}, [r0]
100
101# CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f]
102vst20.32 {q0, q1}, [r0]!
103
104# CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f]
105vst20.32 {q0, q1}, [r11]
106
107# CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf]
108vst20.32 {q5, q6}, [r0]!
109
110# CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f]
111vst21.32 {q0, q1}, [r0]
112
113# CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
114vst21.32 {q3, q4}, [r0]!
115
116# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
117vld20.8 {q0, q1}, [sp]!
118
119# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
120vld20.64 {q0, q1}, [r0]
121
122# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
123vld20.32 {q0, q2}, [r0]
124
125# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of two consecutive q-registers in range [q0,q7]
126vld20.32 {q0, q1, q2}, [r0]
127
128# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of two consecutive q-registers in range [q0,q7]
129vld20.32 {q0}, [r0]
130
131# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
132vld20.32 q0, q1, [r0]
133
134# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
135vld20.32 {q7, q8}, [r0]
136
137# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
138vld20.32 {d0, d1}, [r0]
139
140# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
141vld22.32 {q0, q1}, [r0]
142
143# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
144vld20.32 {q0, q1}, [pc]
145
146# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
147vld20.32 {q0, q1}, [r0, #4]
148
149# CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
150vld40.8 {q0, q1, q2, q3}, [r0]
151
152# CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
153vld40.8 {q0, q1, q2, q3}, [r0]!
154
155# CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e]
156vld40.8 {q0, q1, q2, q3}, [r11]
157
158# CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e]
159vld40.8 {q3, q4, q5, q6}, [r0]!
160
161# CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
162vld41.8 {q0, q1, q2, q3}, [r0]
163
164# CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
165vld41.8 {q4, q5, q6, q7}, [r0]!
166
167# CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
168vld42.8 {q0, q1, q2, q3}, [r0]
169
170# CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e]
171vld42.8 {q0, q1, q2, q3}, [r0]!
172
173# CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e]
174vld43.8 {q0, q1, q2, q3}, [r0]
175
176# CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
177vld43.8 {q4, q5, q6, q7}, [r0]!
178
179# CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e]
180vld40.16 {q0, q1, q2, q3}, [r0]
181
182# CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e]
183vld40.16 {q0, q1, q2, q3}, [r0]!
184
185# CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e]
186vld40.16 {q0, q1, q2, q3}, [r11]
187
188# CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e]
189vld40.16 {q3, q4, q5, q6}, [r0]!
190
191# CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e]
192vld41.16 {q0, q1, q2, q3}, [r0]
193
194# CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
195vld41.16 {q4, q5, q6, q7}, [r0]!
196
197# CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e]
198vld42.16 {q0, q1, q2, q3}, [r0]
199
200# CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e]
201vld42.16 {q0, q1, q2, q3}, [r0]!
202
203# CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e]
204vld43.16 {q0, q1, q2, q3}, [r0]
205
206# CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e]
207vld43.16 {q4, q5, q6, q7}, [r0]!
208
209# CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f]
210vld40.32 {q0, q1, q2, q3}, [r0]
211
212# CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f]
213vld40.32 {q0, q1, q2, q3}, [r0]!
214
215# CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f]
216vld40.32 {q0, q1, q2, q3}, [r11]
217
218# CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f]
219vld40.32 {q3, q4, q5, q6}, [r0]!
220
221# CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f]
222vld41.32 {q0, q1, q2, q3}, [r0]
223
224# CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f]
225vld41.32 {q4, q5, q6, q7}, [r0]!
226
227# CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f]
228vld42.32 {q0, q1, q2, q3}, [r0]
229
230# CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f]
231vld42.32 {q0, q1, q2, q3}, [r0]!
232
233# CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f]
234vld43.32 {q0, q1, q2, q3}, [r0]
235
236# CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f]
237vld43.32 {q4, q5, q6, q7}, [r0]!
238
239# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
240vld40.64 {q0, q1, q2, q3}, [r0]
241
242# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
243vld40.32 {q0, q2, q3, q4}, [r0]
244
245# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
246vld40.32 {q0, q1, q2, q3, q4}, [r0]
247
248# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
249vld40.32 {q0, q1}, [r0]
250
251# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
252vld40.32 {q0, q1, q2}, [r0]
253
254# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
255vld40.32 q0, q1, q2, q3, [r0]
256
257# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
258vld40.32 {q5, q6, q7, q8}, [r0]
259
260# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
261vld40.32 {d0, d1, d2, d3}, [r0]
262
263# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
264vld44.32 {q0, q1, q2, q3}, [r0]
265
266# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
267vld40.32 {q0, q1, q2, q3}, [pc]
268
269# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
270vld40.32 {q0, q1, q2, q3}, [r0, #4]
271