1# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases -show-encoding \
2# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \
4# RUN:     | llvm-objdump --mattr=+f -M no-aliases -d -r - \
5# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
6#
7# RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \
8# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
9
10# CHECK-ASM-AND-OBJ: fcvt.l.s a0, ft0, dyn
11# CHECK-ASM: encoding: [0x53,0x75,0x20,0xc0]
12# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
13fcvt.l.s a0, ft0, dyn
14# CHECK-ASM-AND-OBJ: fcvt.lu.s a1, ft1, dyn
15# CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc0]
16# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
17fcvt.lu.s a1, ft1, dyn
18# CHECK-ASM-AND-OBJ: fcvt.s.l ft2, a2, dyn
19# CHECK-ASM: encoding: [0x53,0x71,0x26,0xd0]
20# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
21fcvt.s.l ft2, a2, dyn
22# CHECK-ASM-AND-OBJ: fcvt.s.lu ft3, a3, dyn
23# CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd0]
24# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
25fcvt.s.lu ft3, a3, dyn
26
27# Rounding modes
28# CHECK-ASM-AND-OBJ: fcvt.l.s a4, ft4, rne
29# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
30fcvt.l.s a4, ft4, rne
31# CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz
32# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
33fcvt.lu.s a5, ft5, rtz
34# CHECK-ASM-AND-OBJ: fcvt.s.l ft6, a6, rdn
35# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
36fcvt.s.l ft6, a6, rdn
37# CHECK-ASM-AND-OBJ: fcvt.s.lu ft7, a7, rup
38# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
39fcvt.s.lu ft7, a7, rup
40