1; RUN: opt -S -instcombine < %s | FileCheck %s 2 3target triple = "x86_64-apple-macosx10.6.6" 4 5define zeroext i16 @foo1(i32 %on_off) { 6; CHECK-LABEL: @foo1( 7; CHECK-NEXT: [[ON_OFF_TR:%.*]] = trunc i32 %on_off to i16 8; CHECK-NEXT: [[TMP1:%.*]] = shl i16 [[ON_OFF_TR]], 1 9; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -2 10; CHECK-NEXT: ret i16 [[CONV]] 11; 12 %on_off.addr = alloca i32, align 4 13 %a = alloca i32, align 4 14 store i32 %on_off, i32* %on_off.addr, align 4 15 %tmp = load i32, i32* %on_off.addr, align 4 16 %sub = sub i32 1, %tmp 17 %mul = mul i32 %sub, -2 18 store i32 %mul, i32* %a, align 4 19 %tmp1 = load i32, i32* %a, align 4 20 %conv = trunc i32 %tmp1 to i16 21 ret i16 %conv 22} 23 24define zeroext i16 @foo2(i32 %on_off, i32 %q) { 25; CHECK-LABEL: @foo2( 26; CHECK-NEXT: [[SUBA:%.*]] = sub i32 %on_off, %q 27; CHECK-NEXT: [[SUBA_TR:%.*]] = trunc i32 [[SUBA]] to i16 28; CHECK-NEXT: [[CONV:%.*]] = shl i16 [[SUBA_TR]], 2 29; CHECK-NEXT: ret i16 [[CONV]] 30; 31 %on_off.addr = alloca i32, align 4 32 %q.addr = alloca i32, align 4 33 %a = alloca i32, align 4 34 store i32 %on_off, i32* %on_off.addr, align 4 35 store i32 %q, i32* %q.addr, align 4 36 %tmp = load i32, i32* %q.addr, align 4 37 %tmp1 = load i32, i32* %on_off.addr, align 4 38 %sub = sub i32 %tmp, %tmp1 39 %mul = mul i32 %sub, -4 40 store i32 %mul, i32* %a, align 4 41 %tmp2 = load i32, i32* %a, align 4 42 %conv = trunc i32 %tmp2 to i16 43 ret i16 %conv 44} 45 46define zeroext i16 @foo3(i32 %on_off) { 47; CHECK-LABEL: @foo3( 48; CHECK-NEXT: [[ON_OFF_TR:%.*]] = trunc i32 %on_off to i16 49; CHECK-NEXT: [[TMP1:%.*]] = shl i16 [[ON_OFF_TR]], 2 50; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -28 51; CHECK-NEXT: ret i16 [[CONV]] 52; 53 %on_off.addr = alloca i32, align 4 54 %a = alloca i32, align 4 55 store i32 %on_off, i32* %on_off.addr, align 4 56 %tmp = load i32, i32* %on_off.addr, align 4 57 %sub = sub i32 7, %tmp 58 %mul = mul i32 %sub, -4 59 store i32 %mul, i32* %a, align 4 60 %tmp1 = load i32, i32* %a, align 4 61 %conv = trunc i32 %tmp1 to i16 62 ret i16 %conv 63} 64 65