1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instcombine -S | FileCheck %s
3
4define i64 @zext(i32 %x, i32 %y, i32 %z) {
5; CHECK-LABEL: @zext(
6; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
7; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[Z:%.*]]
8; CHECK-NEXT:    [[R:%.*]] = zext i32 [[SEL]] to i64
9; CHECK-NEXT:    ret i64 [[R]]
10;
11  %cmp = icmp eq i32 %x, %y
12  %sel = select i1 %cmp, i32 0, i32 %z
13  %r = zext i32 %sel to i64
14  ret i64 %r
15}
16
17define <2 x i32> @zext_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
18; CHECK-LABEL: @zext_vec(
19; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <2 x i8> [[X:%.*]], [[Y:%.*]]
20; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[Z:%.*]], <2 x i8> <i8 42, i8 7>
21; CHECK-NEXT:    [[R:%.*]] = zext <2 x i8> [[SEL]] to <2 x i32>
22; CHECK-NEXT:    ret <2 x i32> [[R]]
23;
24  %cmp = icmp ugt <2 x i8> %x, %y
25  %sel = select <2 x i1> %cmp, <2 x i8> %z, <2 x i8> <i8 42, i8 7>
26  %r = zext <2 x i8> %sel to <2 x i32>
27  ret <2 x i32> %r
28}
29
30define i64 @sext(i8 %x, i8 %y, i8 %z) {
31; CHECK-LABEL: @sext(
32; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[X:%.*]], [[Y:%.*]]
33; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i8 42, i8 [[Z:%.*]]
34; CHECK-NEXT:    [[R:%.*]] = sext i8 [[SEL]] to i64
35; CHECK-NEXT:    ret i64 [[R]]
36;
37  %cmp = icmp ult i8 %x, %y
38  %sel = select i1 %cmp, i8 42, i8 %z
39  %r = sext i8 %sel to i64
40  ret i64 %r
41}
42
43define <2 x i32> @sext_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
44; CHECK-LABEL: @sext_vec(
45; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <2 x i8> [[X:%.*]], [[Y:%.*]]
46; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[Z:%.*]], <2 x i8> <i8 42, i8 7>
47; CHECK-NEXT:    [[R:%.*]] = sext <2 x i8> [[SEL]] to <2 x i32>
48; CHECK-NEXT:    ret <2 x i32> [[R]]
49;
50  %cmp = icmp ugt <2 x i8> %x, %y
51  %sel = select <2 x i1> %cmp, <2 x i8> %z, <2 x i8> <i8 42, i8 7>
52  %r = sext <2 x i8> %sel to <2 x i32>
53  ret <2 x i32> %r
54}
55
56define i16 @trunc(i32 %x, i32 %y, i32 %z) {
57; CHECK-LABEL: @trunc(
58; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]]
59; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[Z:%.*]] to i16
60; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP]], i16 42, i16 [[TMP1]]
61; CHECK-NEXT:    ret i16 [[R]]
62;
63  %cmp = icmp ult i32 %x, %y
64  %sel = select i1 %cmp, i32 42, i32 %z
65  %r = trunc i32 %sel to i16
66  ret i16 %r
67}
68
69define <2 x i32> @trunc_vec(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
70; CHECK-LABEL: @trunc_vec(
71; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <2 x i64> [[X:%.*]], [[Y:%.*]]
72; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[Z:%.*]], <2 x i64> <i64 42, i64 7>
73; CHECK-NEXT:    [[R:%.*]] = trunc <2 x i64> [[SEL]] to <2 x i32>
74; CHECK-NEXT:    ret <2 x i32> [[R]]
75;
76  %cmp = icmp ugt <2 x i64> %x, %y
77  %sel = select <2 x i1> %cmp, <2 x i64> %z, <2 x i64> <i64 42, i64 7>
78  %r = trunc <2 x i64> %sel to <2 x i32>
79  ret <2 x i32> %r
80}
81
82define double @fpext(float %x, float %y, float %z) {
83; CHECK-LABEL: @fpext(
84; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[X:%.*]], [[Y:%.*]]
85; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], float 1.700000e+01, float [[Z:%.*]]
86; CHECK-NEXT:    [[R:%.*]] = fpext float [[SEL]] to double
87; CHECK-NEXT:    ret double [[R]]
88;
89  %cmp = fcmp oeq float %x, %y
90  %sel = select i1 %cmp, float 17.0, float %z
91  %r = fpext float %sel to double
92  ret double %r
93}
94
95define <2 x double> @fpext_vec(<2 x float> %x, <2 x float> %y, <2 x float> %z) {
96; CHECK-LABEL: @fpext_vec(
97; CHECK-NEXT:    [[CMP:%.*]] = fcmp ugt <2 x float> [[X:%.*]], [[Y:%.*]]
98; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x float> [[Z:%.*]], <2 x float> <float 4.200000e+01, float -2.000000e+00>
99; CHECK-NEXT:    [[R:%.*]] = fpext <2 x float> [[SEL]] to <2 x double>
100; CHECK-NEXT:    ret <2 x double> [[R]]
101;
102  %cmp = fcmp ugt <2 x float> %x, %y
103  %sel = select <2 x i1> %cmp, <2 x float> %z, <2 x float> <float 42.0, float -2.0>
104  %r = fpext <2 x float> %sel to <2 x double>
105  ret <2 x double> %r
106}
107
108define float @fptrunc(double %x, double %y, double %z) {
109; CHECK-LABEL: @fptrunc(
110; CHECK-NEXT:    [[CMP:%.*]] = fcmp ult double [[X:%.*]], [[Y:%.*]]
111; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], double 4.200000e+01, double [[Z:%.*]]
112; CHECK-NEXT:    [[R:%.*]] = fptrunc double [[SEL]] to float
113; CHECK-NEXT:    ret float [[R]]
114;
115  %cmp = fcmp ult double %x, %y
116  %sel = select i1 %cmp, double 42.0, double %z
117  %r = fptrunc double %sel to float
118  ret float %r
119}
120
121define <2 x float> @fptrunc_vec(<2 x double> %x, <2 x double> %y, <2 x double> %z) {
122; CHECK-LABEL: @fptrunc_vec(
123; CHECK-NEXT:    [[CMP:%.*]] = fcmp oge <2 x double> [[X:%.*]], [[Y:%.*]]
124; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x double> [[Z:%.*]], <2 x double> <double -4.200000e+01, double 1.200000e+01>
125; CHECK-NEXT:    [[R:%.*]] = fptrunc <2 x double> [[SEL]] to <2 x float>
126; CHECK-NEXT:    ret <2 x float> [[R]]
127;
128  %cmp = fcmp oge <2 x double> %x, %y
129  %sel = select <2 x i1> %cmp, <2 x double> %z, <2 x double> <double -42.0, double 12.0>
130  %r = fptrunc <2 x double> %sel to <2 x float>
131  ret <2 x float> %r
132}
133
134