1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -instcombine < %s | FileCheck %s
3
4define void @insert_store(<16 x i8>* %q, i8 zeroext %s) {
5; CHECK-LABEL: @insert_store(
6; CHECK-NEXT:  entry:
7; CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
8; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 3
9; CHECK-NEXT:    store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16
10; CHECK-NEXT:    ret void
11;
12entry:
13  %0 = load <16 x i8>, <16 x i8>* %q
14  %vecins = insertelement <16 x i8> %0, i8 %s, i32 3
15  store <16 x i8> %vecins, <16 x i8>* %q
16  ret void
17}
18
19define void @single_shuffle_store(<4 x i32>* %a, i32 %b) {
20; CHECK-LABEL: @single_shuffle_store(
21; CHECK-NEXT:  entry:
22; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A:%.*]], align 16
23; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[B:%.*]], i32 1
24; CHECK-NEXT:    store <4 x i32> [[TMP1]], <4 x i32>* [[A]], align 16, !nontemporal !0
25; CHECK-NEXT:    ret void
26;
27entry:
28  %0 = load <4 x i32>, <4 x i32>* %a
29  %1 = insertelement <4 x i32> %0, i32 %b, i32 1
30  %2 = shufflevector <4 x i32> %0, <4 x i32> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
31  store <4 x i32> %2, <4 x i32>* %a, !nontemporal !0
32  ret void
33}
34
35define void @volatile_update(<16 x i8>* %q, <16 x i8>* %p, i8 zeroext %s) {
36; CHECK-LABEL: @volatile_update(
37; CHECK-NEXT:  entry:
38; CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
39; CHECK-NEXT:    [[VECINS0:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 3
40; CHECK-NEXT:    store volatile <16 x i8> [[VECINS0]], <16 x i8>* [[Q]], align 16
41; CHECK-NEXT:    [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* [[P:%.*]], align 16
42; CHECK-NEXT:    [[VECINS1:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[S]], i32 1
43; CHECK-NEXT:    store <16 x i8> [[VECINS1]], <16 x i8>* [[P]], align 16
44; CHECK-NEXT:    ret void
45;
46entry:
47  %0 = load <16 x i8>, <16 x i8>* %q
48  %vecins0 = insertelement <16 x i8> %0, i8 %s, i32 3
49  store volatile <16 x i8> %vecins0, <16 x i8>* %q
50
51  %1 = load volatile <16 x i8>, <16 x i8>* %p
52  %vecins1 = insertelement <16 x i8> %1, i8 %s, i32 1
53  store <16 x i8> %vecins1, <16 x i8>* %p
54  ret void
55}
56
57define void @insert_store_addr_differ(<16 x i8>* %p, <16 x i8>* %q, i8 %s) {
58; CHECK-LABEL: @insert_store_addr_differ(
59; CHECK-NEXT:  entry:
60; CHECK-NEXT:    [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16
61; CHECK-NEXT:    [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
62; CHECK-NEXT:    store <16 x i8> [[INS]], <16 x i8>* [[Q:%.*]], align 16
63; CHECK-NEXT:    ret void
64;
65entry:
66  %ld = load <16 x i8>, <16 x i8>* %p
67  %ins = insertelement <16 x i8> %ld, i8 %s, i32 3
68  store <16 x i8> %ins, <16 x i8>* %q
69  ret void
70}
71
72define void @insert_store_mem_modify(<16 x i8>* %p, <16 x i8>* %q, <16 x i8>* noalias %r, i8 %s) {
73; CHECK-LABEL: @insert_store_mem_modify(
74; CHECK-NEXT:  entry:
75; CHECK-NEXT:    [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16
76; CHECK-NEXT:    store <16 x i8> zeroinitializer, <16 x i8>* [[Q:%.*]], align 16
77; CHECK-NEXT:    [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
78; CHECK-NEXT:    store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16
79; CHECK-NEXT:    [[LD2:%.*]] = load <16 x i8>, <16 x i8>* [[Q]], align 16
80; CHECK-NEXT:    store <16 x i8> zeroinitializer, <16 x i8>* [[R:%.*]], align 16
81; CHECK-NEXT:    [[INS2:%.*]] = insertelement <16 x i8> [[LD2]], i8 [[S]], i32 7
82; CHECK-NEXT:    store <16 x i8> [[INS2]], <16 x i8>* [[Q]], align 16
83; CHECK-NEXT:    ret void
84;
85entry:
86  %ld = load <16 x i8>, <16 x i8>* %p
87  store <16 x i8> zeroinitializer, <16 x i8>* %q
88  %ins = insertelement <16 x i8> %ld, i8 %s, i32 3
89  store <16 x i8> %ins, <16 x i8>* %p
90
91  %ld2 = load <16 x i8>, <16 x i8>* %q
92  store <16 x i8> zeroinitializer, <16 x i8>* %r
93  %ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7
94  store <16 x i8> %ins2, <16 x i8>* %q
95  ret void
96}
97
98!0 = !{}
99