1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -instcombine < %s | FileCheck %s
3
4define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
5; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
6; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
7; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 60
8; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
9; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
10; CHECK-NEXT:    ret i64 [[TMP4]]
11;
12  %1 = and i32 %x, 15
13  %2 = shl nuw nsw i32 %1, 2
14  %3 = zext i32 %2 to i64
15  %4 = icmp eq i32 %1, 0
16  %5 = ashr i64 %y, %3
17  %6 = select i1 %4, i64 %y, i64 %5
18  ret i64 %6
19}
20
21define i64 @sel_false_val_is_a_masked_shl_of_true_val2(i32 %x, i64 %y) {
22; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val2(
23; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
24; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 60
25; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
26; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
27; CHECK-NEXT:    ret i64 [[TMP4]]
28;
29  %1 = and i32 %x, 15
30  %2 = shl nuw nsw i32 %1, 2
31  %3 = zext i32 %2 to i64
32  %4 = icmp eq i32 %2, 0
33  %5 = ashr i64 %y, %3
34  %6 = select i1 %4, i64 %y, i64 %5
35  ret i64 %6
36}
37
38define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
39; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
40; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
41; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 15
42; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
43; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
44; CHECK-NEXT:    ret i64 [[TMP4]]
45;
46  %1 = and i32 %x, 60
47  %2 = lshr i32 %1, 2
48  %3 = zext i32 %2 to i64
49  %4 = icmp eq i32 %1, 0
50  %5 = ashr i64 %y, %3
51  %6 = select i1 %4, i64 %y, i64 %5
52  ret i64 %6
53}
54
55define i64 @sel_false_val_is_a_masked_lshr_of_true_val2(i32 %x, i64 %y) {
56; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val2(
57; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
58; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 15
59; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
60; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
61; CHECK-NEXT:    ret i64 [[TMP4]]
62;
63  %1 = and i32 %x, 60
64  %2 = lshr i32 %1, 2
65  %3 = zext i32 %2 to i64
66  %4 = icmp eq i32 %2, 0
67  %5 = ashr i64 %y, %3
68  %6 = select i1 %4, i64 %y, i64 %5
69  ret i64 %6
70}
71
72define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
73; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
74; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
75; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
76; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
77; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
78; CHECK-NEXT:    ret i64 [[TMP4]]
79;
80  %1 = and i32 %x, -2147483588
81  %2 = ashr i32 %1, 2
82  %3 = zext i32 %2 to i64
83  %4 = icmp eq i32 %1, 0
84  %5 = ashr i64 %y, %3
85  %6 = select i1 %4, i64 %y, i64 %5
86  ret i64 %6
87}
88
89define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {
90; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(
91; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
92; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
93; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
94; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
95; CHECK-NEXT:    ret i64 [[TMP4]]
96;
97  %1 = and i32 %x, -2147483588
98  %2 = ashr i32 %1, 2
99  %3 = zext i32 %2 to i64
100  %4 = icmp eq i32 %2, 0
101  %5 = ashr i64 %y, %3
102  %6 = select i1 %4, i64 %y, i64 %5
103  ret i64 %6
104}
105
106