1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instcombine -S | FileCheck %s
3
4target datalayout = "n8:16:32:64"
5
6declare void @use(i32)
7
8define i32 @sextinreg(i32 %x) {
9; CHECK-LABEL: @sextinreg(
10; CHECK-NEXT:    [[SEXT:%.*]] = shl i32 [[X:%.*]], 16
11; CHECK-NEXT:    [[T3:%.*]] = ashr exact i32 [[SEXT]], 16
12; CHECK-NEXT:    ret i32 [[T3]]
13;
14  %t1 = and i32 %x, 65535
15  %t2 = xor i32 %t1, -32768
16  %t3 = add i32 %t2, 32768
17  ret i32 %t3
18}
19
20define i32 @sextinreg_extra_use(i32 %x) {
21; CHECK-LABEL: @sextinreg_extra_use(
22; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 65535
23; CHECK-NEXT:    [[T2:%.*]] = xor i32 [[T1]], -32768
24; CHECK-NEXT:    call void @use(i32 [[T2]])
25; CHECK-NEXT:    [[T3:%.*]] = add nsw i32 [[T2]], 32768
26; CHECK-NEXT:    ret i32 [[T3]]
27;
28  %t1 = and i32 %x, 65535
29  %t2 = xor i32 %t1, -32768
30  call void @use(i32 %t2)
31  %t3 = add i32 %t2, 32768
32  ret i32 %t3
33}
34
35define <2 x i32> @sextinreg_splat(<2 x i32> %x) {
36; CHECK-LABEL: @sextinreg_splat(
37; CHECK-NEXT:    [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], <i32 16, i32 16>
38; CHECK-NEXT:    [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16>
39; CHECK-NEXT:    ret <2 x i32> [[T3]]
40;
41  %t1 = and <2 x i32> %x, <i32 65535, i32 65535>
42  %t2 = xor <2 x i32> %t1, <i32 -32768, i32 -32768>
43  %t3 = add <2 x i32> %t2, <i32 32768, i32 32768>
44  ret <2 x i32> %t3
45}
46
47define i32 @sextinreg_alt(i32 %x) {
48; CHECK-LABEL: @sextinreg_alt(
49; CHECK-NEXT:    [[SEXT:%.*]] = shl i32 [[X:%.*]], 16
50; CHECK-NEXT:    [[T3:%.*]] = ashr exact i32 [[SEXT]], 16
51; CHECK-NEXT:    ret i32 [[T3]]
52;
53  %t1 = and i32 %x, 65535
54  %t2 = xor i32 %t1, 32768
55  %t3 = add i32 %t2, -32768
56  ret i32 %t3
57}
58
59define <2 x i32> @sextinreg_alt_splat(<2 x i32> %x) {
60; CHECK-LABEL: @sextinreg_alt_splat(
61; CHECK-NEXT:    [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], <i32 16, i32 16>
62; CHECK-NEXT:    [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16>
63; CHECK-NEXT:    ret <2 x i32> [[T3]]
64;
65  %t1 = and <2 x i32> %x, <i32 65535, i32 65535>
66  %t2 = xor <2 x i32> %t1, <i32 32768, i32 32768>
67  %t3 = add <2 x i32> %t2, <i32 -32768, i32 -32768>
68  ret <2 x i32> %t3
69}
70
71define i32 @sext(i16 %P) {
72; CHECK-LABEL: @sext(
73; CHECK-NEXT:    [[T5:%.*]] = sext i16 [[P:%.*]] to i32
74; CHECK-NEXT:    ret i32 [[T5]]
75;
76  %t1 = zext i16 %P to i32
77  %t4 = xor i32 %t1, 32768
78  %t5 = add i32 %t4, -32768
79  ret i32 %t5
80}
81
82define i32 @sext_extra_use(i16 %P) {
83; CHECK-LABEL: @sext_extra_use(
84; CHECK-NEXT:    [[TMP1:%.*]] = xor i16 [[P:%.*]], -32768
85; CHECK-NEXT:    [[T4:%.*]] = zext i16 [[TMP1]] to i32
86; CHECK-NEXT:    call void @use(i32 [[T4]])
87; CHECK-NEXT:    [[T5:%.*]] = sext i16 [[P]] to i32
88; CHECK-NEXT:    ret i32 [[T5]]
89;
90  %t1 = zext i16 %P to i32
91  %t4 = xor i32 %t1, 32768
92  call void @use(i32 %t4)
93  %t5 = add i32 %t4, -32768
94  ret i32 %t5
95}
96
97define <2 x i32> @sext_splat(<2 x i16> %P) {
98; CHECK-LABEL: @sext_splat(
99; CHECK-NEXT:    [[T5:%.*]] = sext <2 x i16> [[P:%.*]] to <2 x i32>
100; CHECK-NEXT:    ret <2 x i32> [[T5]]
101;
102  %t1 = zext <2 x i16> %P to <2 x i32>
103  %t4 = xor <2 x i32> %t1, <i32 32768, i32 32768>
104  %t5 = add <2 x i32> %t4, <i32 -32768, i32 -32768>
105  ret <2 x i32> %t5
106}
107
108define i32 @sextinreg2(i32 %x) {
109; CHECK-LABEL: @sextinreg2(
110; CHECK-NEXT:    [[SEXT:%.*]] = shl i32 [[X:%.*]], 24
111; CHECK-NEXT:    [[T3:%.*]] = ashr exact i32 [[SEXT]], 24
112; CHECK-NEXT:    ret i32 [[T3]]
113;
114  %t1 = and i32 %x, 255
115  %t2 = xor i32 %t1, 128
116  %t3 = add i32 %t2, -128
117  ret i32 %t3
118}
119
120define <2 x i32> @sextinreg2_splat(<2 x i32> %x) {
121; CHECK-LABEL: @sextinreg2_splat(
122; CHECK-NEXT:    [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], <i32 24, i32 24>
123; CHECK-NEXT:    [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 24, i32 24>
124; CHECK-NEXT:    ret <2 x i32> [[T3]]
125;
126  %t1 = and <2 x i32> %x, <i32 255, i32 255>
127  %t2 = xor <2 x i32> %t1, <i32 128, i32 128>
128  %t3 = add <2 x i32> %t2, <i32 -128, i32 -128>
129  ret <2 x i32> %t3
130}
131
132define i32 @test5(i32 %x) {
133; CHECK-LABEL: @test5(
134; CHECK-NEXT:    [[T2:%.*]] = shl i32 [[X:%.*]], 16
135; CHECK-NEXT:    [[T4:%.*]] = ashr exact i32 [[T2]], 16
136; CHECK-NEXT:    ret i32 [[T4]]
137;
138  %t2 = shl i32 %x, 16
139  %t4 = ashr i32 %t2, 16
140  ret i32 %t4
141}
142
143;  If the shift amount equals the difference in width of the destination
144;  and source scalar types:
145;  ashr (shl (zext X), C), C --> sext X
146
147define i32 @test6(i16 %P) {
148; CHECK-LABEL: @test6(
149; CHECK-NEXT:    [[T5:%.*]] = sext i16 [[P:%.*]] to i32
150; CHECK-NEXT:    ret i32 [[T5]]
151;
152  %t1 = zext i16 %P to i32
153  %sext1 = shl i32 %t1, 16
154  %t5 = ashr i32 %sext1, 16
155  ret i32 %t5
156}
157
158; Vectors should get the same fold as above.
159
160define <2 x i32> @test6_splat_vec(<2 x i12> %P) {
161; CHECK-LABEL: @test6_splat_vec(
162; CHECK-NEXT:    [[ASHR:%.*]] = sext <2 x i12> [[P:%.*]] to <2 x i32>
163; CHECK-NEXT:    ret <2 x i32> [[ASHR]]
164;
165  %z = zext <2 x i12> %P to <2 x i32>
166  %shl = shl <2 x i32> %z, <i32 20, i32 20>
167  %ashr = ashr <2 x i32> %shl, <i32 20, i32 20>
168  ret <2 x i32> %ashr
169}
170
171define i32 @ashr(i32 %x) {
172; CHECK-LABEL: @ashr(
173; CHECK-NEXT:    [[SUB:%.*]] = ashr i32 [[X:%.*]], 5
174; CHECK-NEXT:    ret i32 [[SUB]]
175;
176  %shr = lshr i32 %x, 5
177  %xor = xor i32 %shr, 67108864
178  %sub = add i32 %xor, -67108864
179  ret i32 %sub
180}
181
182define <2 x i32> @ashr_splat(<2 x i32> %x) {
183; CHECK-LABEL: @ashr_splat(
184; CHECK-NEXT:    [[SUB:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 5, i32 5>
185; CHECK-NEXT:    ret <2 x i32> [[SUB]]
186;
187  %shr = lshr <2 x i32> %x, <i32 5, i32 5>
188  %xor = xor <2 x i32> %shr, <i32 67108864, i32 67108864>
189  %sub = add <2 x i32> %xor, <i32 -67108864, i32 -67108864>
190  ret <2 x i32> %sub
191}
192