1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instcombine -S | FileCheck %s
3
4define <4 x i32> @test_v4i32_splatconst_pow2(<4 x i32> %a0) {
5; CHECK-LABEL: @test_v4i32_splatconst_pow2(
6; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1>
7; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
8;
9  %1 = udiv <4 x i32> %a0, <i32 2, i32 2, i32 2, i32 2>
10  ret <4 x i32> %1
11}
12
13define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) {
14; CHECK-LABEL: @test_v4i32_const_pow2(
15; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[A0:%.*]], <i32 0, i32 1, i32 2, i32 3>
16; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
17;
18  %1 = udiv <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
19  ret <4 x i32> %1
20}
21
22; X udiv C, where C >= signbit
23define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) {
24; CHECK-LABEL: @test_v4i32_negconstsplat(
25; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -4, i32 -4, i32 -4>
26; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
27; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
28;
29  %1 = udiv <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3>
30  ret <4 x i32> %1
31}
32
33define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) {
34; CHECK-LABEL: @test_v4i32_negconst(
35; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -6, i32 -8, i32 -10>
36; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
37; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
38;
39  %1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
40  ret <4 x i32> %1
41}
42
43define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) {
44; CHECK-LABEL: @test_v4i32_negconst_undef(
45; CHECK-NEXT:    ret <4 x i32> undef
46;
47  %1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef>
48  ret <4 x i32> %1
49}
50
51; X udiv (C1 << N), where C1 is "1<<C2"  -->  X >> (N+C2)
52define <4 x i32> @test_v4i32_shl_splatconst_pow2(<4 x i32> %a0, <4 x i32> %a1) {
53; CHECK-LABEL: @test_v4i32_shl_splatconst_pow2(
54; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[A1:%.*]], <i32 2, i32 2, i32 2, i32 2>
55; CHECK-NEXT:    [[TMP2:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP1]]
56; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
57;
58  %1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %a1
59  %2 = udiv <4 x i32> %a0, %1
60  ret <4 x i32> %2
61}
62
63define <4 x i32> @test_v4i32_shl_const_pow2(<4 x i32> %a0, <4 x i32> %a1) {
64; CHECK-LABEL: @test_v4i32_shl_const_pow2(
65; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[A1:%.*]], <i32 2, i32 3, i32 4, i32 5>
66; CHECK-NEXT:    [[TMP2:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP1]]
67; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
68;
69  %1 = shl <4 x i32> <i32 4, i32 8, i32 16, i32 32>, %a1
70  %2 = udiv <4 x i32> %a0, %1
71  ret <4 x i32> %2
72}
73
74; X udiv (zext (C1 << N)), where C1 is "1<<C2"  -->  X >> (N+C2)
75define <4 x i32> @test_v4i32_zext_shl_splatconst_pow2(<4 x i32> %a0, <4 x i16> %a1) {
76; CHECK-LABEL: @test_v4i32_zext_shl_splatconst_pow2(
77; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i16> [[A1:%.*]], <i16 2, i16 2, i16 2, i16 2>
78; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
79; CHECK-NEXT:    [[TMP3:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP2]]
80; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
81;
82  %1 = shl <4 x i16> <i16 4, i16 4, i16 4, i16 4>, %a1
83  %2 = zext <4 x i16> %1 to <4 x i32>
84  %3 = udiv <4 x i32> %a0, %2
85  ret <4 x i32> %3
86}
87
88define <4 x i32> @test_v4i32_zext_shl_const_pow2(<4 x i32> %a0, <4 x i16> %a1) {
89; CHECK-LABEL: @test_v4i32_zext_shl_const_pow2(
90; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i16> [[A1:%.*]], <i16 2, i16 3, i16 4, i16 5>
91; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
92; CHECK-NEXT:    [[TMP3:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP2]]
93; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
94;
95  %1 = shl <4 x i16> <i16 4, i16 8, i16 16, i16 32>, %a1
96  %2 = zext <4 x i16> %1 to <4 x i32>
97  %3 = udiv <4 x i32> %a0, %2
98  ret <4 x i32> %3
99}
100