1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instsimplify -S -o - | FileCheck %s
3
4declare i32 @llvm.fshl.i32(i32, i32, i32)
5declare i32 @llvm.fshr.i32(i32, i32, i32)
6declare i7 @llvm.fshl.i7(i7, i7, i7)
7declare i7 @llvm.fshr.i7(i7, i7, i7)
8declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
9declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
10
11; extract(concat(0x12345678, 0xABCDEF01) << 5) = 0x468ACF15
12
13define i32 @fshl_i32() {
14; CHECK-LABEL: @fshl_i32(
15; CHECK-NEXT:    ret i32 1183502101
16;
17  %f = call i32 @llvm.fshl.i32(i32 305419896, i32 2882400001, i32 5)
18  ret i32 %f
19}
20
21; extract(concat(0x12345678, 0xABCDEF01) >> 5) = 0xC55E6F78
22; Try an oversized shift to test modulo functionality.
23
24define i32 @fshr_i32() {
25; CHECK-LABEL: @fshr_i32(
26; CHECK-NEXT:    ret i32 -983666824
27;
28  %f = call i32 @llvm.fshr.i32(i32 305419896, i32 2882400001, i32 37)
29  ret i32 %f
30}
31
32; Use a weird type.
33; Try an oversized shift to test modulo functionality.
34
35; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
36
37define i7 @fshl_i7() {
38; CHECK-LABEL: @fshl_i7(
39; CHECK-NEXT:    ret i7 -61
40;
41  %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 9)
42  ret i7 %f
43}
44
45; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
46; Try an oversized shift to test modulo functionality.
47
48define i7 @fshr_i7() {
49; CHECK-LABEL: @fshr_i7(
50; CHECK-NEXT:    ret i7 31
51;
52  %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 16)
53  ret i7 %f
54}
55
56; Vectors are folded by handling each scalar element individually, so this is the equivalent of 4 scalar tests:
57; extract(concat(0x00, 0xFF) << 0) = 0x00
58; extract(concat(0xFF, 0x00) << 0) = 0xFF
59; extract(concat(0x10, 0x55) << 1) = 0x20
60; extract(concat(0x11, 0xAA) << 2) = 0x46
61
62define <4 x i8> @fshl_v4i8() {
63; CHECK-LABEL: @fshl_v4i8(
64; CHECK-NEXT:    ret <4 x i8> <i8 0, i8 -1, i8 32, i8 70>
65;
66  %f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 0, i8 -1, i8 16, i8 17>, <4 x i8> <i8 -1, i8 0, i8 85, i8 170>, <4 x i8> <i8 0, i8 8, i8 9, i8 10>)
67  ret <4 x i8> %f
68}
69
70; Vectors are folded by handling each scalar element individually, so this is the equivalent of 4 scalar tests:
71; extract(concat(0x00, 0xFF) >> 0) = 0xFF
72; extract(concat(0xFF, 0x00) >> 0) = 0x00
73; extract(concat(0x10, 0x55) >> 1) = 0x2A
74; extract(concat(0x11, 0xAA) >> 2) = 0x6A
75
76define <4 x i8> @fshr_v4i8() {
77; CHECK-LABEL: @fshr_v4i8(
78; CHECK-NEXT:    ret <4 x i8> <i8 -1, i8 0, i8 42, i8 106>
79;
80  %f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 0, i8 -1, i8 16, i8 17>, <4 x i8> <i8 -1, i8 0, i8 85, i8 170>, <4 x i8> <i8 0, i8 8, i8 9, i8 10>)
81  ret <4 x i8> %f
82}
83
84; Undef handling
85
86define i32 @fshl_scalar_all_undef() {
87; CHECK-LABEL: @fshl_scalar_all_undef(
88; CHECK-NEXT:    ret i32 undef
89;
90  %f = call i32 @llvm.fshl.i32(i32 undef, i32 undef, i32 undef)
91  ret i32 %f
92}
93
94define i32 @fshr_scalar_all_undef() {
95; CHECK-LABEL: @fshr_scalar_all_undef(
96; CHECK-NEXT:    ret i32 undef
97;
98  %f = call i32 @llvm.fshr.i32(i32 undef, i32 undef, i32 undef)
99  ret i32 %f
100}
101
102define i32 @fshl_scalar_undef_shamt() {
103; CHECK-LABEL: @fshl_scalar_undef_shamt(
104; CHECK-NEXT:    ret i32 1
105;
106  %f = call i32 @llvm.fshl.i32(i32 1, i32 2, i32 undef)
107  ret i32 %f
108}
109
110define i32 @fshr_scalar_undef_shamt() {
111; CHECK-LABEL: @fshr_scalar_undef_shamt(
112; CHECK-NEXT:    ret i32 2
113;
114  %f = call i32 @llvm.fshr.i32(i32 1, i32 2, i32 undef)
115  ret i32 %f
116}
117
118define i32 @fshl_scalar_undef_ops() {
119; CHECK-LABEL: @fshl_scalar_undef_ops(
120; CHECK-NEXT:    ret i32 undef
121;
122  %f = call i32 @llvm.fshl.i32(i32 undef, i32 undef, i32 7)
123  ret i32 %f
124}
125
126define i32 @fshr_scalar_undef_ops() {
127; CHECK-LABEL: @fshr_scalar_undef_ops(
128; CHECK-NEXT:    ret i32 undef
129;
130  %f = call i32 @llvm.fshr.i32(i32 undef, i32 undef, i32 7)
131  ret i32 %f
132}
133
134define i32 @fshl_scalar_undef_op1_zero_shift() {
135; CHECK-LABEL: @fshl_scalar_undef_op1_zero_shift(
136; CHECK-NEXT:    ret i32 undef
137;
138  %f = call i32 @llvm.fshl.i32(i32 undef, i32 1, i32 0)
139  ret i32 %f
140}
141
142define i32 @fshl_scalar_undef_op2_zero_shift() {
143; CHECK-LABEL: @fshl_scalar_undef_op2_zero_shift(
144; CHECK-NEXT:    ret i32 1
145;
146  %f = call i32 @llvm.fshl.i32(i32 1, i32 undef, i32 32)
147  ret i32 %f
148}
149
150define i32 @fshr_scalar_undef_op1_zero_shift() {
151; CHECK-LABEL: @fshr_scalar_undef_op1_zero_shift(
152; CHECK-NEXT:    ret i32 1
153;
154  %f = call i32 @llvm.fshr.i32(i32 undef, i32 1, i32 64)
155  ret i32 %f
156}
157
158define i32 @fshr_scalar_undef_op2_zero_shift() {
159; CHECK-LABEL: @fshr_scalar_undef_op2_zero_shift(
160; CHECK-NEXT:    ret i32 undef
161;
162  %f = call i32 @llvm.fshr.i32(i32 1, i32 undef, i32 0)
163  ret i32 %f
164}
165
166define i32 @fshl_scalar_undef_op1_nonzero_shift() {
167; CHECK-LABEL: @fshl_scalar_undef_op1_nonzero_shift(
168; CHECK-NEXT:    ret i32 255
169;
170  %f = call i32 @llvm.fshl.i32(i32 undef, i32 -1, i32 8)
171  ret i32 %f
172}
173
174define i32 @fshl_scalar_undef_op2_nonzero_shift() {
175; CHECK-LABEL: @fshl_scalar_undef_op2_nonzero_shift(
176; CHECK-NEXT:    ret i32 -256
177;
178  %f = call i32 @llvm.fshl.i32(i32 -1, i32 undef, i32 8)
179  ret i32 %f
180}
181
182define i32 @fshr_scalar_undef_op1_nonzero_shift() {
183; CHECK-LABEL: @fshr_scalar_undef_op1_nonzero_shift(
184; CHECK-NEXT:    ret i32 16777215
185;
186  %f = call i32 @llvm.fshr.i32(i32 undef, i32 -1, i32 8)
187  ret i32 %f
188}
189
190define i32 @fshr_scalar_undef_op2_nonzero_shift() {
191; CHECK-LABEL: @fshr_scalar_undef_op2_nonzero_shift(
192; CHECK-NEXT:    ret i32 -16777216
193;
194  %f = call i32 @llvm.fshr.i32(i32 -1, i32 undef, i32 8)
195  ret i32 %f
196}
197
198; Undef/Undef/Undef; 1/2/Undef; Undef/Undef/3; Undef/1/0
199define <4 x i8> @fshl_vector_mix1() {
200; CHECK-LABEL: @fshl_vector_mix1(
201; CHECK-NEXT:    ret <4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>
202;
203  %f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>, <4 x i8> <i8 undef, i8 2, i8 undef, i8 1>, <4 x i8> <i8 undef, i8 undef, i8 3, i8 0>)
204  ret <4 x i8> %f
205}
206
207; 1/Undef/8; Undef/-1/2; -1/Undef/2; 7/8/4
208define <4 x i8> @fshl_vector_mix2() {
209; CHECK-LABEL: @fshl_vector_mix2(
210; CHECK-NEXT:    ret <4 x i8> <i8 1, i8 3, i8 -4, i8 112>
211;
212  %f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 1, i8 undef, i8 -1, i8 7>, <4 x i8> <i8 undef, i8 -1, i8 undef, i8 8>, <4 x i8> <i8 8, i8 2, i8 2, i8 4>)
213  ret <4 x i8> %f
214}
215
216; Undef/Undef/Undef; 1/2/Undef; Undef/Undef/3; Undef/1/0
217define <4 x i8> @fshr_vector_mix1() {
218; CHECK-LABEL: @fshr_vector_mix1(
219; CHECK-NEXT:    ret <4 x i8> <i8 undef, i8 2, i8 undef, i8 1>
220;
221  %f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>, <4 x i8> <i8 undef, i8 2, i8 undef, i8 1>, <4 x i8> <i8 undef, i8 undef, i8 3, i8 0>)
222  ret <4 x i8> %f
223}
224
225; 1/Undef/8; Undef/-1/2; -1/Undef/2; 7/8/4
226define <4 x i8> @fshr_vector_mix2() {
227; CHECK-LABEL: @fshr_vector_mix2(
228; CHECK-NEXT:    ret <4 x i8> <i8 undef, i8 63, i8 -64, i8 112>
229;
230  %f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 1, i8 undef, i8 -1, i8 7>, <4 x i8> <i8 undef, i8 -1, i8 undef, i8 8>, <4 x i8> <i8 8, i8 2, i8 2, i8 4>)
231  ret <4 x i8> %f
232}
233