1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instsimplify -S | FileCheck %s 3 4define i32 @zero_dividend(i32 %A) { 5; CHECK-LABEL: @zero_dividend( 6; CHECK-NEXT: ret i32 0 7; 8 %B = urem i32 0, %A 9 ret i32 %B 10} 11 12define <2 x i32> @zero_dividend_vector(<2 x i32> %A) { 13; CHECK-LABEL: @zero_dividend_vector( 14; CHECK-NEXT: ret <2 x i32> zeroinitializer 15; 16 %B = srem <2 x i32> zeroinitializer, %A 17 ret <2 x i32> %B 18} 19 20define <2 x i32> @zero_dividend_vector_undef_elt(<2 x i32> %A) { 21; CHECK-LABEL: @zero_dividend_vector_undef_elt( 22; CHECK-NEXT: ret <2 x i32> zeroinitializer 23; 24 %B = urem <2 x i32> <i32 undef, i32 0>, %A 25 ret <2 x i32> %B 26} 27 28; Division-by-zero is poison. UB in any vector lane means the whole op is poison. 29 30define <2 x i8> @srem_zero_elt_vec_constfold(<2 x i8> %x) { 31; CHECK-LABEL: @srem_zero_elt_vec_constfold( 32; CHECK-NEXT: ret <2 x i8> poison 33; 34 %rem = srem <2 x i8> <i8 1, i8 2>, <i8 0, i8 -42> 35 ret <2 x i8> %rem 36} 37 38define <2 x i8> @urem_zero_elt_vec_constfold(<2 x i8> %x) { 39; CHECK-LABEL: @urem_zero_elt_vec_constfold( 40; CHECK-NEXT: ret <2 x i8> poison 41; 42 %rem = urem <2 x i8> <i8 1, i8 2>, <i8 42, i8 0> 43 ret <2 x i8> %rem 44} 45 46; TODO: instsimplify should fold these to poison 47define <2 x i8> @srem_zero_elt_vec(<2 x i8> %x) { 48; CHECK-LABEL: @srem_zero_elt_vec( 49; CHECK-NEXT: ret <2 x i8> undef 50; 51 %rem = srem <2 x i8> %x, <i8 -42, i8 0> 52 ret <2 x i8> %rem 53} 54 55define <2 x i8> @urem_zero_elt_vec(<2 x i8> %x) { 56; CHECK-LABEL: @urem_zero_elt_vec( 57; CHECK-NEXT: ret <2 x i8> undef 58; 59 %rem = urem <2 x i8> %x, <i8 0, i8 42> 60 ret <2 x i8> %rem 61} 62 63define <2 x i8> @srem_undef_elt_vec(<2 x i8> %x) { 64; CHECK-LABEL: @srem_undef_elt_vec( 65; CHECK-NEXT: ret <2 x i8> undef 66; 67 %rem = srem <2 x i8> %x, <i8 -42, i8 undef> 68 ret <2 x i8> %rem 69} 70 71define <2 x i8> @urem_undef_elt_vec(<2 x i8> %x) { 72; CHECK-LABEL: @urem_undef_elt_vec( 73; CHECK-NEXT: ret <2 x i8> undef 74; 75 %rem = urem <2 x i8> %x, <i8 undef, i8 42> 76 ret <2 x i8> %rem 77} 78 79; Division-by-zero is undef. UB in any vector lane means the whole op is undef. 80; Thus, we can simplify this: if any element of 'y' is 0, we can do anything. 81; Therefore, assume that all elements of 'y' must be 1. 82 83define <2 x i1> @srem_bool_vec(<2 x i1> %x, <2 x i1> %y) { 84; CHECK-LABEL: @srem_bool_vec( 85; CHECK-NEXT: ret <2 x i1> zeroinitializer 86; 87 %rem = srem <2 x i1> %x, %y 88 ret <2 x i1> %rem 89} 90 91define <2 x i1> @urem_bool_vec(<2 x i1> %x, <2 x i1> %y) { 92; CHECK-LABEL: @urem_bool_vec( 93; CHECK-NEXT: ret <2 x i1> zeroinitializer 94; 95 %rem = urem <2 x i1> %x, %y 96 ret <2 x i1> %rem 97} 98 99define <2 x i32> @zext_bool_urem_divisor_vec(<2 x i1> %x, <2 x i32> %y) { 100; CHECK-LABEL: @zext_bool_urem_divisor_vec( 101; CHECK-NEXT: ret <2 x i32> zeroinitializer 102; 103 %ext = zext <2 x i1> %x to <2 x i32> 104 %r = urem <2 x i32> %y, %ext 105 ret <2 x i32> %r 106} 107 108define i32 @zext_bool_srem_divisor(i1 %x, i32 %y) { 109; CHECK-LABEL: @zext_bool_srem_divisor( 110; CHECK-NEXT: ret i32 0 111; 112 %ext = zext i1 %x to i32 113 %r = srem i32 %y, %ext 114 ret i32 %r 115} 116 117define i32 @select1(i32 %x, i1 %b) { 118; CHECK-LABEL: @select1( 119; CHECK-NEXT: ret i32 0 120; 121 %rhs = select i1 %b, i32 %x, i32 1 122 %rem = srem i32 %x, %rhs 123 ret i32 %rem 124} 125 126define i32 @select2(i32 %x, i1 %b) { 127; CHECK-LABEL: @select2( 128; CHECK-NEXT: ret i32 0 129; 130 %rhs = select i1 %b, i32 %x, i32 1 131 %rem = urem i32 %x, %rhs 132 ret i32 %rem 133} 134 135define i32 @rem1(i32 %x, i32 %n) { 136; CHECK-LABEL: @rem1( 137; CHECK-NEXT: [[MOD:%.*]] = srem i32 [[X:%.*]], [[N:%.*]] 138; CHECK-NEXT: ret i32 [[MOD]] 139; 140 %mod = srem i32 %x, %n 141 %mod1 = srem i32 %mod, %n 142 ret i32 %mod1 143} 144 145define i32 @rem2(i32 %x, i32 %n) { 146; CHECK-LABEL: @rem2( 147; CHECK-NEXT: [[MOD:%.*]] = urem i32 [[X:%.*]], [[N:%.*]] 148; CHECK-NEXT: ret i32 [[MOD]] 149; 150 %mod = urem i32 %x, %n 151 %mod1 = urem i32 %mod, %n 152 ret i32 %mod1 153} 154 155define i32 @rem3(i32 %x, i32 %n) { 156; CHECK-LABEL: @rem3( 157; CHECK-NEXT: [[MOD:%.*]] = srem i32 [[X:%.*]], [[N:%.*]] 158; CHECK-NEXT: [[MOD1:%.*]] = urem i32 [[MOD]], [[N]] 159; CHECK-NEXT: ret i32 [[MOD1]] 160; 161 %mod = srem i32 %x, %n 162 %mod1 = urem i32 %mod, %n 163 ret i32 %mod1 164} 165 166define i32 @urem_dividend_known_smaller_than_constant_divisor(i32 %x) { 167; CHECK-LABEL: @urem_dividend_known_smaller_than_constant_divisor( 168; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 250 169; CHECK-NEXT: ret i32 [[AND]] 170; 171 %and = and i32 %x, 250 172 %r = urem i32 %and, 251 173 ret i32 %r 174} 175 176define i32 @not_urem_dividend_known_smaller_than_constant_divisor(i32 %x) { 177; CHECK-LABEL: @not_urem_dividend_known_smaller_than_constant_divisor( 178; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 251 179; CHECK-NEXT: [[R:%.*]] = urem i32 [[AND]], 251 180; CHECK-NEXT: ret i32 [[R]] 181; 182 %and = and i32 %x, 251 183 %r = urem i32 %and, 251 184 ret i32 %r 185} 186 187define i32 @urem_constant_dividend_known_smaller_than_divisor(i32 %x) { 188; CHECK-LABEL: @urem_constant_dividend_known_smaller_than_divisor( 189; CHECK-NEXT: ret i32 250 190; 191 %or = or i32 %x, 251 192 %r = urem i32 250, %or 193 ret i32 %r 194} 195 196define i32 @not_urem_constant_dividend_known_smaller_than_divisor(i32 %x) { 197; CHECK-LABEL: @not_urem_constant_dividend_known_smaller_than_divisor( 198; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], 251 199; CHECK-NEXT: [[R:%.*]] = urem i32 251, [[OR]] 200; CHECK-NEXT: ret i32 [[R]] 201; 202 %or = or i32 %x, 251 203 %r = urem i32 251, %or 204 ret i32 %r 205} 206 207; This would require computing known bits on both x and y. Is it worth doing? 208 209define i32 @urem_dividend_known_smaller_than_divisor(i32 %x, i32 %y) { 210; CHECK-LABEL: @urem_dividend_known_smaller_than_divisor( 211; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 250 212; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 251 213; CHECK-NEXT: [[R:%.*]] = urem i32 [[AND]], [[OR]] 214; CHECK-NEXT: ret i32 [[R]] 215; 216 %and = and i32 %x, 250 217 %or = or i32 %y, 251 218 %r = urem i32 %and, %or 219 ret i32 %r 220} 221 222define i32 @not_urem_dividend_known_smaller_than_divisor(i32 %x, i32 %y) { 223; CHECK-LABEL: @not_urem_dividend_known_smaller_than_divisor( 224; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 251 225; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 251 226; CHECK-NEXT: [[R:%.*]] = urem i32 [[AND]], [[OR]] 227; CHECK-NEXT: ret i32 [[R]] 228; 229 %and = and i32 %x, 251 230 %or = or i32 %y, 251 231 %r = urem i32 %and, %or 232 ret i32 %r 233} 234 235declare i32 @external() 236 237define i32 @rem4() { 238; CHECK-LABEL: @rem4( 239; CHECK-NEXT: [[CALL:%.*]] = call i32 @external(), [[RNG0:!range !.*]] 240; CHECK-NEXT: ret i32 [[CALL]] 241; 242 %call = call i32 @external(), !range !0 243 %urem = urem i32 %call, 3 244 ret i32 %urem 245} 246 247!0 = !{i32 0, i32 3} 248 249define i32 @rem5(i32 %x, i32 %y) { 250; CHECK-LABEL: @rem5( 251; CHECK-NEXT: ret i32 0 252; 253 %shl = shl nsw i32 %x, %y 254 %mod = srem i32 %shl, %x 255 ret i32 %mod 256} 257 258define <2 x i32> @rem6(<2 x i32> %x, <2 x i32> %y) { 259; CHECK-LABEL: @rem6( 260; CHECK-NEXT: ret <2 x i32> zeroinitializer 261; 262 %shl = shl nsw <2 x i32> %x, %y 263 %mod = srem <2 x i32> %shl, %x 264 ret <2 x i32> %mod 265} 266 267; make sure the previous fold doesn't take place for wrapped shifts 268 269define i32 @rem7(i32 %x, i32 %y) { 270; CHECK-LABEL: @rem7( 271; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]] 272; CHECK-NEXT: [[MOD:%.*]] = srem i32 [[SHL]], [[X]] 273; CHECK-NEXT: ret i32 [[MOD]] 274; 275 %shl = shl i32 %x, %y 276 %mod = srem i32 %shl, %x 277 ret i32 %mod 278} 279 280define i32 @rem8(i32 %x, i32 %y) { 281; CHECK-LABEL: @rem8( 282; CHECK-NEXT: ret i32 0 283; 284 %shl = shl nuw i32 %x, %y 285 %mod = urem i32 %shl, %x 286 ret i32 %mod 287} 288 289define <2 x i32> @rem9(<2 x i32> %x, <2 x i32> %y) { 290; CHECK-LABEL: @rem9( 291; CHECK-NEXT: ret <2 x i32> zeroinitializer 292; 293 %shl = shl nuw <2 x i32> %x, %y 294 %mod = urem <2 x i32> %shl, %x 295 ret <2 x i32> %mod 296} 297 298; make sure the previous fold doesn't take place for wrapped shifts 299 300define i32 @rem10(i32 %x, i32 %y) { 301; CHECK-LABEL: @rem10( 302; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]] 303; CHECK-NEXT: [[MOD:%.*]] = urem i32 [[SHL]], [[X]] 304; CHECK-NEXT: ret i32 [[MOD]] 305; 306 %shl = shl i32 %x, %y 307 %mod = urem i32 %shl, %x 308 ret i32 %mod 309} 310 311define i32 @srem_with_sext_bool_divisor(i1 %x, i32 %y) { 312; CHECK-LABEL: @srem_with_sext_bool_divisor( 313; CHECK-NEXT: ret i32 0 314; 315 %s = sext i1 %x to i32 316 %r = srem i32 %y, %s 317 ret i32 %r 318} 319 320define <2 x i32> @srem_with_sext_bool_divisor_vec(<2 x i1> %x, <2 x i32> %y) { 321; CHECK-LABEL: @srem_with_sext_bool_divisor_vec( 322; CHECK-NEXT: ret <2 x i32> zeroinitializer 323; 324 %s = sext <2 x i1> %x to <2 x i32> 325 %r = srem <2 x i32> %y, %s 326 ret <2 x i32> %r 327} 328 329define i8 @srem_minusone_divisor() { 330; CHECK-LABEL: @srem_minusone_divisor( 331; CHECK-NEXT: ret i8 poison 332; 333 %v = srem i8 -128, -1 334 ret i8 %v 335} 336 337define i32 @poison(i32 %x) { 338; CHECK-LABEL: @poison( 339; CHECK-NEXT: ret i32 poison 340; 341 %v = urem i32 %x, poison 342 ret i32 %v 343} 344 345; TODO: this should be poison 346 347define i32 @poison2(i32 %x) { 348; CHECK-LABEL: @poison2( 349; CHECK-NEXT: ret i32 0 350; 351 %v = urem i32 poison, %x 352 ret i32 %v 353} 354