1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -loop-vectorize -instcombine -simplifycfg -tail-predication=enabled < %s -S -o - | FileCheck %s
3
4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
5target triple = "thumbv8.1m.main-arm-none-eabi"
6
7define i64 @add_i64_i64(i64* nocapture readonly %x, i32 %n) #0 {
8; CHECK-LABEL: @add_i64_i64(
9; CHECK-NEXT:  entry:
10; CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
11; CHECK-NEXT:    br i1 [[CMP6]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
12; CHECK:       for.body:
13; CHECK-NEXT:    [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
14; CHECK-NEXT:    [[R_07:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
15; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i64, i64* [[X:%.*]], i32 [[I_08]]
16; CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[ARRAYIDX]], align 8
17; CHECK-NEXT:    [[ADD]] = add nsw i64 [[TMP0]], [[R_07]]
18; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_08]], 1
19; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
20; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
21; CHECK:       for.cond.cleanup:
22; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
23; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
24;
25entry:
26  %cmp6 = icmp sgt i32 %n, 0
27  br i1 %cmp6, label %for.body, label %for.cond.cleanup
28
29for.body:                                         ; preds = %entry, %for.body
30  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
31  %r.07 = phi i64 [ %add, %for.body ], [ 0, %entry ]
32  %arrayidx = getelementptr inbounds i64, i64* %x, i32 %i.08
33  %0 = load i64, i64* %arrayidx, align 8
34  %add = add nsw i64 %0, %r.07
35  %inc = add nuw nsw i32 %i.08, 1
36  %exitcond = icmp eq i32 %inc, %n
37  br i1 %exitcond, label %for.cond.cleanup, label %for.body
38
39for.cond.cleanup:                                 ; preds = %for.body, %entry
40  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
41  ret i64 %r.0.lcssa
42}
43
44; FIXME: 4x
45define i64 @add_i32_i64(i32* nocapture readonly %x, i32 %n) #0 {
46; CHECK-LABEL: @add_i32_i64(
47; CHECK-NEXT:  entry:
48; CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
49; CHECK-NEXT:    br i1 [[CMP6]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
50; CHECK:       for.body:
51; CHECK-NEXT:    [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
52; CHECK-NEXT:    [[R_07:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
53; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[X:%.*]], i32 [[I_08]]
54; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
55; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
56; CHECK-NEXT:    [[ADD]] = add nsw i64 [[R_07]], [[CONV]]
57; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_08]], 1
58; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
59; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
60; CHECK:       for.cond.cleanup:
61; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
62; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
63;
64entry:
65  %cmp6 = icmp sgt i32 %n, 0
66  br i1 %cmp6, label %for.body, label %for.cond.cleanup
67
68for.body:                                         ; preds = %entry, %for.body
69  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
70  %r.07 = phi i64 [ %add, %for.body ], [ 0, %entry ]
71  %arrayidx = getelementptr inbounds i32, i32* %x, i32 %i.08
72  %0 = load i32, i32* %arrayidx, align 4
73  %conv = sext i32 %0 to i64
74  %add = add nsw i64 %r.07, %conv
75  %inc = add nuw nsw i32 %i.08, 1
76  %exitcond = icmp eq i32 %inc, %n
77  br i1 %exitcond, label %for.cond.cleanup, label %for.body
78
79for.cond.cleanup:                                 ; preds = %for.body, %entry
80  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
81  ret i64 %r.0.lcssa
82}
83
84; FIXME: 4x ?
85define i64 @add_i16_i64(i16* nocapture readonly %x, i32 %n) #0 {
86; CHECK-LABEL: @add_i16_i64(
87; CHECK-NEXT:  entry:
88; CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
89; CHECK-NEXT:    br i1 [[CMP6]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
90; CHECK:       for.body:
91; CHECK-NEXT:    [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
92; CHECK-NEXT:    [[R_07:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
93; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[I_08]]
94; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* [[ARRAYIDX]], align 2
95; CHECK-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i64
96; CHECK-NEXT:    [[ADD]] = add nsw i64 [[R_07]], [[CONV]]
97; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_08]], 1
98; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
99; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
100; CHECK:       for.cond.cleanup:
101; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
102; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
103;
104entry:
105  %cmp6 = icmp sgt i32 %n, 0
106  br i1 %cmp6, label %for.body, label %for.cond.cleanup
107
108for.body:                                         ; preds = %entry, %for.body
109  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
110  %r.07 = phi i64 [ %add, %for.body ], [ 0, %entry ]
111  %arrayidx = getelementptr inbounds i16, i16* %x, i32 %i.08
112  %0 = load i16, i16* %arrayidx, align 2
113  %conv = sext i16 %0 to i64
114  %add = add nsw i64 %r.07, %conv
115  %inc = add nuw nsw i32 %i.08, 1
116  %exitcond = icmp eq i32 %inc, %n
117  br i1 %exitcond, label %for.cond.cleanup, label %for.body
118
119for.cond.cleanup:                                 ; preds = %for.body, %entry
120  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
121  ret i64 %r.0.lcssa
122}
123
124; FIXME: 4x ?
125define i64 @add_i8_i64(i8* nocapture readonly %x, i32 %n) #0 {
126; CHECK-LABEL: @add_i8_i64(
127; CHECK-NEXT:  entry:
128; CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
129; CHECK-NEXT:    br i1 [[CMP6]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
130; CHECK:       for.body:
131; CHECK-NEXT:    [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
132; CHECK-NEXT:    [[R_07:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
133; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[I_08]]
134; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
135; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[TMP0]] to i64
136; CHECK-NEXT:    [[ADD]] = add nuw nsw i64 [[R_07]], [[CONV]]
137; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_08]], 1
138; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
139; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
140; CHECK:       for.cond.cleanup:
141; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
142; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
143;
144entry:
145  %cmp6 = icmp sgt i32 %n, 0
146  br i1 %cmp6, label %for.body, label %for.cond.cleanup
147
148for.body:                                         ; preds = %entry, %for.body
149  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
150  %r.07 = phi i64 [ %add, %for.body ], [ 0, %entry ]
151  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.08
152  %0 = load i8, i8* %arrayidx, align 1
153  %conv = zext i8 %0 to i64
154  %add = add nuw nsw i64 %r.07, %conv
155  %inc = add nuw nsw i32 %i.08, 1
156  %exitcond = icmp eq i32 %inc, %n
157  br i1 %exitcond, label %for.cond.cleanup, label %for.body
158
159for.cond.cleanup:                                 ; preds = %for.body, %entry
160  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
161  ret i64 %r.0.lcssa
162}
163
164define i32 @add_i32_i32(i32* nocapture readonly %x, i32 %n) #0 {
165; CHECK-LABEL: @add_i32_i32(
166; CHECK-NEXT:  entry:
167; CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
168; CHECK-NEXT:    br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
169; CHECK:       vector.ph:
170; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 3
171; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4
172; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
173; CHECK:       vector.body:
174; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
175; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
176; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX]], i32 [[N]])
177; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[X:%.*]], i32 [[INDEX]]
178; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to <4 x i32>*
179; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[TMP1]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> undef)
180; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer
181; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
182; CHECK-NEXT:    [[TMP4]] = add i32 [[TMP3]], [[VEC_PHI]]
183; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 4
184; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
185; CHECK-NEXT:    br i1 [[TMP5]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
186; CHECK:       for.cond.cleanup:
187; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP4]], [[VECTOR_BODY]] ]
188; CHECK-NEXT:    ret i32 [[R_0_LCSSA]]
189;
190entry:
191  %cmp6 = icmp sgt i32 %n, 0
192  br i1 %cmp6, label %for.body, label %for.cond.cleanup
193
194for.body:                                         ; preds = %entry, %for.body
195  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
196  %r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
197  %arrayidx = getelementptr inbounds i32, i32* %x, i32 %i.08
198  %0 = load i32, i32* %arrayidx, align 4
199  %add = add nsw i32 %0, %r.07
200  %inc = add nuw nsw i32 %i.08, 1
201  %exitcond = icmp eq i32 %inc, %n
202  br i1 %exitcond, label %for.cond.cleanup, label %for.body
203
204for.cond.cleanup:                                 ; preds = %for.body, %entry
205  %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
206  ret i32 %r.0.lcssa
207}
208
209; FIXME: 8x
210define i32 @add_i16_i32(i16* nocapture readonly %x, i32 %n) #0 {
211; CHECK-LABEL: @add_i16_i32(
212; CHECK-NEXT:  entry:
213; CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
214; CHECK-NEXT:    br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
215; CHECK:       vector.ph:
216; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 3
217; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4
218; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
219; CHECK:       vector.body:
220; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
221; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
222; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX]], i32 [[N]])
223; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[INDEX]]
224; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[TMP0]] to <4 x i16>*
225; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* [[TMP1]], i32 2, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i16> undef)
226; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i16> [[WIDE_MASKED_LOAD]] to <4 x i32>
227; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> [[TMP2]], <4 x i32> zeroinitializer
228; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
229; CHECK-NEXT:    [[TMP5]] = add i32 [[TMP4]], [[VEC_PHI]]
230; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 4
231; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
232; CHECK-NEXT:    br i1 [[TMP6]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP2:!llvm.loop !.*]]
233; CHECK:       for.cond.cleanup:
234; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP5]], [[VECTOR_BODY]] ]
235; CHECK-NEXT:    ret i32 [[R_0_LCSSA]]
236;
237entry:
238  %cmp6 = icmp sgt i32 %n, 0
239  br i1 %cmp6, label %for.body, label %for.cond.cleanup
240
241for.body:                                         ; preds = %entry, %for.body
242  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
243  %r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
244  %arrayidx = getelementptr inbounds i16, i16* %x, i32 %i.08
245  %0 = load i16, i16* %arrayidx, align 2
246  %conv = sext i16 %0 to i32
247  %add = add nsw i32 %r.07, %conv
248  %inc = add nuw nsw i32 %i.08, 1
249  %exitcond = icmp eq i32 %inc, %n
250  br i1 %exitcond, label %for.cond.cleanup, label %for.body
251
252for.cond.cleanup:                                 ; preds = %for.body, %entry
253  %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
254  ret i32 %r.0.lcssa
255}
256
257; FIXME: 16x
258define i32 @add_i8_i32(i8* nocapture readonly %x, i32 %n) #0 {
259; CHECK-LABEL: @add_i8_i32(
260; CHECK-NEXT:  entry:
261; CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
262; CHECK-NEXT:    br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
263; CHECK:       vector.ph:
264; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 3
265; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4
266; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
267; CHECK:       vector.body:
268; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
269; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
270; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX]], i32 [[N]])
271; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[INDEX]]
272; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
273; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* [[TMP1]], i32 1, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i8> undef)
274; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i8> [[WIDE_MASKED_LOAD]] to <4 x i32>
275; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> [[TMP2]], <4 x i32> zeroinitializer
276; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
277; CHECK-NEXT:    [[TMP5]] = add i32 [[TMP4]], [[VEC_PHI]]
278; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 4
279; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
280; CHECK-NEXT:    br i1 [[TMP6]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP3:!llvm.loop !.*]]
281; CHECK:       for.cond.cleanup:
282; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP5]], [[VECTOR_BODY]] ]
283; CHECK-NEXT:    ret i32 [[R_0_LCSSA]]
284;
285entry:
286  %cmp6 = icmp sgt i32 %n, 0
287  br i1 %cmp6, label %for.body, label %for.cond.cleanup
288
289for.body:                                         ; preds = %entry, %for.body
290  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
291  %r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
292  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.08
293  %0 = load i8, i8* %arrayidx, align 1
294  %conv = zext i8 %0 to i32
295  %add = add nuw nsw i32 %r.07, %conv
296  %inc = add nuw nsw i32 %i.08, 1
297  %exitcond = icmp eq i32 %inc, %n
298  br i1 %exitcond, label %for.cond.cleanup, label %for.body
299
300for.cond.cleanup:                                 ; preds = %for.body, %entry
301  %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
302  ret i32 %r.0.lcssa
303}
304
305define signext i16 @add_i16_i16(i16* nocapture readonly %x, i32 %n) #0 {
306; CHECK-LABEL: @add_i16_i16(
307; CHECK-NEXT:  entry:
308; CHECK-NEXT:    [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0
309; CHECK-NEXT:    br i1 [[CMP8]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
310; CHECK:       vector.ph:
311; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 7
312; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8
313; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
314; CHECK:       vector.body:
315; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
316; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i16 [ 0, [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
317; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 [[INDEX]], i32 [[N]])
318; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[INDEX]]
319; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[TMP0]] to <8 x i16>*
320; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* [[TMP1]], i32 2, <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> undef)
321; CHECK-NEXT:    [[TMP2:%.*]] = select <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> [[WIDE_MASKED_LOAD]], <8 x i16> zeroinitializer
322; CHECK-NEXT:    [[TMP3:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[TMP2]])
323; CHECK-NEXT:    [[TMP4]] = add i16 [[TMP3]], [[VEC_PHI]]
324; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 8
325; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
326; CHECK-NEXT:    br i1 [[TMP5]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP4:!llvm.loop !.*]]
327; CHECK:       for.cond.cleanup:
328; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[TMP4]], [[VECTOR_BODY]] ]
329; CHECK-NEXT:    ret i16 [[R_0_LCSSA]]
330;
331entry:
332  %cmp8 = icmp sgt i32 %n, 0
333  br i1 %cmp8, label %for.body, label %for.cond.cleanup
334
335for.body:                                         ; preds = %entry, %for.body
336  %i.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
337  %r.09 = phi i16 [ %add, %for.body ], [ 0, %entry ]
338  %arrayidx = getelementptr inbounds i16, i16* %x, i32 %i.010
339  %0 = load i16, i16* %arrayidx, align 2
340  %add = add i16 %0, %r.09
341  %inc = add nuw nsw i32 %i.010, 1
342  %exitcond = icmp eq i32 %inc, %n
343  br i1 %exitcond, label %for.cond.cleanup, label %for.body
344
345for.cond.cleanup:                                 ; preds = %for.body, %entry
346  %r.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
347  ret i16 %r.0.lcssa
348}
349
350; FIXME: 16x ?
351define signext i16 @add_i8_i16(i8* nocapture readonly %x, i32 %n) #0 {
352; CHECK-LABEL: @add_i8_i16(
353; CHECK-NEXT:  entry:
354; CHECK-NEXT:    [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0
355; CHECK-NEXT:    br i1 [[CMP8]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
356; CHECK:       vector.ph:
357; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 7
358; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8
359; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
360; CHECK:       vector.body:
361; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
362; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i16 [ 0, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
363; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 [[INDEX]], i32 [[N]])
364; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[INDEX]]
365; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i8>*
366; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* [[TMP1]], i32 1, <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i8> undef)
367; CHECK-NEXT:    [[TMP2:%.*]] = zext <8 x i8> [[WIDE_MASKED_LOAD]] to <8 x i16>
368; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> [[TMP2]], <8 x i16> zeroinitializer
369; CHECK-NEXT:    [[TMP4:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[TMP3]])
370; CHECK-NEXT:    [[TMP5]] = add i16 [[TMP4]], [[VEC_PHI]]
371; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 8
372; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
373; CHECK-NEXT:    br i1 [[TMP6]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP5:!llvm.loop !.*]]
374; CHECK:       for.cond.cleanup:
375; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[TMP5]], [[VECTOR_BODY]] ]
376; CHECK-NEXT:    ret i16 [[R_0_LCSSA]]
377;
378entry:
379  %cmp8 = icmp sgt i32 %n, 0
380  br i1 %cmp8, label %for.body, label %for.cond.cleanup
381
382for.body:                                         ; preds = %entry, %for.body
383  %i.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
384  %r.09 = phi i16 [ %add, %for.body ], [ 0, %entry ]
385  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.010
386  %0 = load i8, i8* %arrayidx, align 1
387  %conv = zext i8 %0 to i16
388  %add = add i16 %r.09, %conv
389  %inc = add nuw nsw i32 %i.010, 1
390  %exitcond = icmp eq i32 %inc, %n
391  br i1 %exitcond, label %for.cond.cleanup, label %for.body
392
393for.cond.cleanup:                                 ; preds = %for.body, %entry
394  %r.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
395  ret i16 %r.0.lcssa
396}
397
398define zeroext i8 @add_i8_i8(i8* nocapture readonly %x, i32 %n) #0 {
399; CHECK-LABEL: @add_i8_i8(
400; CHECK-NEXT:  entry:
401; CHECK-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[N:%.*]], 0
402; CHECK-NEXT:    br i1 [[CMP7]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
403; CHECK:       vector.ph:
404; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 15
405; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16
406; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
407; CHECK:       vector.body:
408; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
409; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i8 [ 0, [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
410; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 [[INDEX]], i32 [[N]])
411; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[INDEX]]
412; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <16 x i8>*
413; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP1]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> undef)
414; CHECK-NEXT:    [[TMP2:%.*]] = select <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> [[WIDE_MASKED_LOAD]], <16 x i8> zeroinitializer
415; CHECK-NEXT:    [[TMP3:%.*]] = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> [[TMP2]])
416; CHECK-NEXT:    [[TMP4]] = add i8 [[TMP3]], [[VEC_PHI]]
417; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 16
418; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
419; CHECK-NEXT:    br i1 [[TMP5]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP6:!llvm.loop !.*]]
420; CHECK:       for.cond.cleanup:
421; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[TMP4]], [[VECTOR_BODY]] ]
422; CHECK-NEXT:    ret i8 [[R_0_LCSSA]]
423;
424entry:
425  %cmp7 = icmp sgt i32 %n, 0
426  br i1 %cmp7, label %for.body, label %for.cond.cleanup
427
428for.body:                                         ; preds = %entry, %for.body
429  %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
430  %r.08 = phi i8 [ %add, %for.body ], [ 0, %entry ]
431  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.09
432  %0 = load i8, i8* %arrayidx, align 1
433  %add = add i8 %0, %r.08
434  %inc = add nuw nsw i32 %i.09, 1
435  %exitcond = icmp eq i32 %inc, %n
436  br i1 %exitcond, label %for.cond.cleanup, label %for.body
437
438for.cond.cleanup:                                 ; preds = %for.body, %entry
439  %r.0.lcssa = phi i8 [ 0, %entry ], [ %add, %for.body ]
440  ret i8 %r.0.lcssa
441}
442
443define i64 @mla_i64_i64(i64* nocapture readonly %x, i64* nocapture readonly %y, i32 %n) #0 {
444; CHECK-LABEL: @mla_i64_i64(
445; CHECK-NEXT:  entry:
446; CHECK-NEXT:    [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0
447; CHECK-NEXT:    br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
448; CHECK:       for.body:
449; CHECK-NEXT:    [[I_010:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
450; CHECK-NEXT:    [[R_09:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
451; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i64, i64* [[X:%.*]], i32 [[I_010]]
452; CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[ARRAYIDX]], align 8
453; CHECK-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, i64* [[Y:%.*]], i32 [[I_010]]
454; CHECK-NEXT:    [[TMP1:%.*]] = load i64, i64* [[ARRAYIDX1]], align 8
455; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP1]], [[TMP0]]
456; CHECK-NEXT:    [[ADD]] = add nsw i64 [[MUL]], [[R_09]]
457; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_010]], 1
458; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
459; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
460; CHECK:       for.cond.cleanup:
461; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
462; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
463;
464entry:
465  %cmp8 = icmp sgt i32 %n, 0
466  br i1 %cmp8, label %for.body, label %for.cond.cleanup
467
468for.body:                                         ; preds = %entry, %for.body
469  %i.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
470  %r.09 = phi i64 [ %add, %for.body ], [ 0, %entry ]
471  %arrayidx = getelementptr inbounds i64, i64* %x, i32 %i.010
472  %0 = load i64, i64* %arrayidx, align 8
473  %arrayidx1 = getelementptr inbounds i64, i64* %y, i32 %i.010
474  %1 = load i64, i64* %arrayidx1, align 8
475  %mul = mul nsw i64 %1, %0
476  %add = add nsw i64 %mul, %r.09
477  %inc = add nuw nsw i32 %i.010, 1
478  %exitcond = icmp eq i32 %inc, %n
479  br i1 %exitcond, label %for.cond.cleanup, label %for.body
480
481for.cond.cleanup:                                 ; preds = %for.body, %entry
482  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
483  ret i64 %r.0.lcssa
484}
485
486define i64 @mla_i32_i64(i32* nocapture readonly %x, i32* nocapture readonly %y, i32 %n) #0 {
487; CHECK-LABEL: @mla_i32_i64(
488; CHECK-NEXT:  entry:
489; CHECK-NEXT:    [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0
490; CHECK-NEXT:    br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
491; CHECK:       for.body:
492; CHECK-NEXT:    [[I_010:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
493; CHECK-NEXT:    [[R_09:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
494; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[X:%.*]], i32 [[I_010]]
495; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
496; CHECK-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[Y:%.*]], i32 [[I_010]]
497; CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4
498; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP1]], [[TMP0]]
499; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[MUL]] to i64
500; CHECK-NEXT:    [[ADD]] = add nsw i64 [[R_09]], [[CONV]]
501; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_010]], 1
502; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
503; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
504; CHECK:       for.cond.cleanup:
505; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
506; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
507;
508entry:
509  %cmp8 = icmp sgt i32 %n, 0
510  br i1 %cmp8, label %for.body, label %for.cond.cleanup
511
512for.body:                                         ; preds = %entry, %for.body
513  %i.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
514  %r.09 = phi i64 [ %add, %for.body ], [ 0, %entry ]
515  %arrayidx = getelementptr inbounds i32, i32* %x, i32 %i.010
516  %0 = load i32, i32* %arrayidx, align 4
517  %arrayidx1 = getelementptr inbounds i32, i32* %y, i32 %i.010
518  %1 = load i32, i32* %arrayidx1, align 4
519  %mul = mul nsw i32 %1, %0
520  %conv = sext i32 %mul to i64
521  %add = add nsw i64 %r.09, %conv
522  %inc = add nuw nsw i32 %i.010, 1
523  %exitcond = icmp eq i32 %inc, %n
524  br i1 %exitcond, label %for.cond.cleanup, label %for.body
525
526for.cond.cleanup:                                 ; preds = %for.body, %entry
527  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
528  ret i64 %r.0.lcssa
529}
530
531define i64 @mla_i16_i64(i16* nocapture readonly %x, i16* nocapture readonly %y, i32 %n) #0 {
532; CHECK-LABEL: @mla_i16_i64(
533; CHECK-NEXT:  entry:
534; CHECK-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[N:%.*]], 0
535; CHECK-NEXT:    br i1 [[CMP10]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
536; CHECK:       for.body:
537; CHECK-NEXT:    [[I_012:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
538; CHECK-NEXT:    [[R_011:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
539; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[I_012]]
540; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* [[ARRAYIDX]], align 2
541; CHECK-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
542; CHECK-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, i16* [[Y:%.*]], i32 [[I_012]]
543; CHECK-NEXT:    [[TMP1:%.*]] = load i16, i16* [[ARRAYIDX1]], align 2
544; CHECK-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
545; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[CONV2]], [[CONV]]
546; CHECK-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL]] to i64
547; CHECK-NEXT:    [[ADD]] = add nsw i64 [[R_011]], [[CONV3]]
548; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_012]], 1
549; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
550; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
551; CHECK:       for.cond.cleanup:
552; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
553; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
554;
555entry:
556  %cmp10 = icmp sgt i32 %n, 0
557  br i1 %cmp10, label %for.body, label %for.cond.cleanup
558
559for.body:                                         ; preds = %entry, %for.body
560  %i.012 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
561  %r.011 = phi i64 [ %add, %for.body ], [ 0, %entry ]
562  %arrayidx = getelementptr inbounds i16, i16* %x, i32 %i.012
563  %0 = load i16, i16* %arrayidx, align 2
564  %conv = sext i16 %0 to i32
565  %arrayidx1 = getelementptr inbounds i16, i16* %y, i32 %i.012
566  %1 = load i16, i16* %arrayidx1, align 2
567  %conv2 = sext i16 %1 to i32
568  %mul = mul nsw i32 %conv2, %conv
569  %conv3 = sext i32 %mul to i64
570  %add = add nsw i64 %r.011, %conv3
571  %inc = add nuw nsw i32 %i.012, 1
572  %exitcond = icmp eq i32 %inc, %n
573  br i1 %exitcond, label %for.cond.cleanup, label %for.body
574
575for.cond.cleanup:                                 ; preds = %for.body, %entry
576  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
577  ret i64 %r.0.lcssa
578}
579
580define i64 @mla_i8_i64(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
581; CHECK-LABEL: @mla_i8_i64(
582; CHECK-NEXT:  entry:
583; CHECK-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[N:%.*]], 0
584; CHECK-NEXT:    br i1 [[CMP10]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
585; CHECK:       for.body:
586; CHECK-NEXT:    [[I_012:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
587; CHECK-NEXT:    [[R_011:%.*]] = phi i64 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
588; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[I_012]]
589; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
590; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[TMP0]] to i32
591; CHECK-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[Y:%.*]], i32 [[I_012]]
592; CHECK-NEXT:    [[TMP1:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1
593; CHECK-NEXT:    [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
594; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[CONV2]], [[CONV]]
595; CHECK-NEXT:    [[CONV3:%.*]] = zext i32 [[MUL]] to i64
596; CHECK-NEXT:    [[ADD]] = add nuw nsw i64 [[R_011]], [[CONV3]]
597; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_012]], 1
598; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
599; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
600; CHECK:       for.cond.cleanup:
601; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD]], [[FOR_BODY]] ]
602; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]
603;
604entry:
605  %cmp10 = icmp sgt i32 %n, 0
606  br i1 %cmp10, label %for.body, label %for.cond.cleanup
607
608for.body:                                         ; preds = %entry, %for.body
609  %i.012 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
610  %r.011 = phi i64 [ %add, %for.body ], [ 0, %entry ]
611  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.012
612  %0 = load i8, i8* %arrayidx, align 1
613  %conv = zext i8 %0 to i32
614  %arrayidx1 = getelementptr inbounds i8, i8* %y, i32 %i.012
615  %1 = load i8, i8* %arrayidx1, align 1
616  %conv2 = zext i8 %1 to i32
617  %mul = mul nuw nsw i32 %conv2, %conv
618  %conv3 = zext i32 %mul to i64
619  %add = add nuw nsw i64 %r.011, %conv3
620  %inc = add nuw nsw i32 %i.012, 1
621  %exitcond = icmp eq i32 %inc, %n
622  br i1 %exitcond, label %for.cond.cleanup, label %for.body
623
624for.cond.cleanup:                                 ; preds = %for.body, %entry
625  %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
626  ret i64 %r.0.lcssa
627}
628
629define i32 @mla_i32_i32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32 %n) #0 {
630; CHECK-LABEL: @mla_i32_i32(
631; CHECK-NEXT:  entry:
632; CHECK-NEXT:    [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0
633; CHECK-NEXT:    br i1 [[CMP8]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
634; CHECK:       vector.ph:
635; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 3
636; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4
637; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
638; CHECK:       vector.body:
639; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
640; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]
641; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX]], i32 [[N]])
642; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[X:%.*]], i32 [[INDEX]]
643; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[TMP0]] to <4 x i32>*
644; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[TMP1]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> undef)
645; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[Y:%.*]], i32 [[INDEX]]
646; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <4 x i32>*
647; CHECK-NEXT:    [[WIDE_MASKED_LOAD1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[TMP3]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> undef)
648; CHECK-NEXT:    [[TMP4:%.*]] = mul nsw <4 x i32> [[WIDE_MASKED_LOAD1]], [[WIDE_MASKED_LOAD]]
649; CHECK-NEXT:    [[TMP5:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> [[TMP4]], <4 x i32> zeroinitializer
650; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
651; CHECK-NEXT:    [[TMP7]] = add i32 [[TMP6]], [[VEC_PHI]]
652; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 4
653; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
654; CHECK-NEXT:    br i1 [[TMP8]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP7:!llvm.loop !.*]]
655; CHECK:       for.cond.cleanup:
656; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP7]], [[VECTOR_BODY]] ]
657; CHECK-NEXT:    ret i32 [[R_0_LCSSA]]
658;
659entry:
660  %cmp8 = icmp sgt i32 %n, 0
661  br i1 %cmp8, label %for.body, label %for.cond.cleanup
662
663for.body:                                         ; preds = %entry, %for.body
664  %i.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
665  %r.09 = phi i32 [ %add, %for.body ], [ 0, %entry ]
666  %arrayidx = getelementptr inbounds i32, i32* %x, i32 %i.010
667  %0 = load i32, i32* %arrayidx, align 4
668  %arrayidx1 = getelementptr inbounds i32, i32* %y, i32 %i.010
669  %1 = load i32, i32* %arrayidx1, align 4
670  %mul = mul nsw i32 %1, %0
671  %add = add nsw i32 %mul, %r.09
672  %inc = add nuw nsw i32 %i.010, 1
673  %exitcond = icmp eq i32 %inc, %n
674  br i1 %exitcond, label %for.cond.cleanup, label %for.body
675
676for.cond.cleanup:                                 ; preds = %for.body, %entry
677  %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
678  ret i32 %r.0.lcssa
679}
680
681define i32 @mla_i16_i32(i16* nocapture readonly %x, i16* nocapture readonly %y, i32 %n) #0 {
682; CHECK-LABEL: @mla_i16_i32(
683; CHECK-NEXT:  entry:
684; CHECK-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0
685; CHECK-NEXT:    br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
686; CHECK:       vector.ph:
687; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 3
688; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4
689; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
690; CHECK:       vector.body:
691; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
692; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]
693; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX]], i32 [[N]])
694; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[INDEX]]
695; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[TMP0]] to <4 x i16>*
696; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* [[TMP1]], i32 2, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i16> undef)
697; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i16> [[WIDE_MASKED_LOAD]] to <4 x i32>
698; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i16, i16* [[Y:%.*]], i32 [[INDEX]]
699; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i16* [[TMP3]] to <4 x i16>*
700; CHECK-NEXT:    [[WIDE_MASKED_LOAD1:%.*]] = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* [[TMP4]], i32 2, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i16> undef)
701; CHECK-NEXT:    [[TMP5:%.*]] = sext <4 x i16> [[WIDE_MASKED_LOAD1]] to <4 x i32>
702; CHECK-NEXT:    [[TMP6:%.*]] = mul nsw <4 x i32> [[TMP5]], [[TMP2]]
703; CHECK-NEXT:    [[TMP7:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> [[TMP6]], <4 x i32> zeroinitializer
704; CHECK-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])
705; CHECK-NEXT:    [[TMP9]] = add i32 [[TMP8]], [[VEC_PHI]]
706; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 4
707; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
708; CHECK-NEXT:    br i1 [[TMP10]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP8:!llvm.loop !.*]]
709; CHECK:       for.cond.cleanup:
710; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP9]], [[VECTOR_BODY]] ]
711; CHECK-NEXT:    ret i32 [[R_0_LCSSA]]
712;
713entry:
714  %cmp9 = icmp sgt i32 %n, 0
715  br i1 %cmp9, label %for.body, label %for.cond.cleanup
716
717for.body:                                         ; preds = %entry, %for.body
718  %i.011 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
719  %r.010 = phi i32 [ %add, %for.body ], [ 0, %entry ]
720  %arrayidx = getelementptr inbounds i16, i16* %x, i32 %i.011
721  %0 = load i16, i16* %arrayidx, align 2
722  %conv = sext i16 %0 to i32
723  %arrayidx1 = getelementptr inbounds i16, i16* %y, i32 %i.011
724  %1 = load i16, i16* %arrayidx1, align 2
725  %conv2 = sext i16 %1 to i32
726  %mul = mul nsw i32 %conv2, %conv
727  %add = add nsw i32 %mul, %r.010
728  %inc = add nuw nsw i32 %i.011, 1
729  %exitcond = icmp eq i32 %inc, %n
730  br i1 %exitcond, label %for.cond.cleanup, label %for.body
731
732for.cond.cleanup:                                 ; preds = %for.body, %entry
733  %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
734  ret i32 %r.0.lcssa
735}
736
737define i32 @mla_i8_i32(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
738; CHECK-LABEL: @mla_i8_i32(
739; CHECK-NEXT:  entry:
740; CHECK-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0
741; CHECK-NEXT:    br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
742; CHECK:       vector.ph:
743; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 3
744; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4
745; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
746; CHECK:       vector.body:
747; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
748; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]
749; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[INDEX]], i32 [[N]])
750; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[INDEX]]
751; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
752; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* [[TMP1]], i32 1, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i8> undef)
753; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i8> [[WIDE_MASKED_LOAD]] to <4 x i32>
754; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[Y:%.*]], i32 [[INDEX]]
755; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>*
756; CHECK-NEXT:    [[WIDE_MASKED_LOAD1:%.*]] = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* [[TMP4]], i32 1, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i8> undef)
757; CHECK-NEXT:    [[TMP5:%.*]] = zext <4 x i8> [[WIDE_MASKED_LOAD1]] to <4 x i32>
758; CHECK-NEXT:    [[TMP6:%.*]] = mul nuw nsw <4 x i32> [[TMP5]], [[TMP2]]
759; CHECK-NEXT:    [[TMP7:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> [[TMP6]], <4 x i32> zeroinitializer
760; CHECK-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])
761; CHECK-NEXT:    [[TMP9]] = add i32 [[TMP8]], [[VEC_PHI]]
762; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 4
763; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
764; CHECK-NEXT:    br i1 [[TMP10]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP9:!llvm.loop !.*]]
765; CHECK:       for.cond.cleanup:
766; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP9]], [[VECTOR_BODY]] ]
767; CHECK-NEXT:    ret i32 [[R_0_LCSSA]]
768;
769entry:
770  %cmp9 = icmp sgt i32 %n, 0
771  br i1 %cmp9, label %for.body, label %for.cond.cleanup
772
773for.body:                                         ; preds = %entry, %for.body
774  %i.011 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
775  %r.010 = phi i32 [ %add, %for.body ], [ 0, %entry ]
776  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.011
777  %0 = load i8, i8* %arrayidx, align 1
778  %conv = zext i8 %0 to i32
779  %arrayidx1 = getelementptr inbounds i8, i8* %y, i32 %i.011
780  %1 = load i8, i8* %arrayidx1, align 1
781  %conv2 = zext i8 %1 to i32
782  %mul = mul nuw nsw i32 %conv2, %conv
783  %add = add nuw nsw i32 %mul, %r.010
784  %inc = add nuw nsw i32 %i.011, 1
785  %exitcond = icmp eq i32 %inc, %n
786  br i1 %exitcond, label %for.cond.cleanup, label %for.body
787
788for.cond.cleanup:                                 ; preds = %for.body, %entry
789  %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
790  ret i32 %r.0.lcssa
791}
792
793define signext i16 @mla_i16_i16(i16* nocapture readonly %x, i16* nocapture readonly %y, i32 %n) #0 {
794; CHECK-LABEL: @mla_i16_i16(
795; CHECK-NEXT:  entry:
796; CHECK-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[N:%.*]], 0
797; CHECK-NEXT:    br i1 [[CMP11]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
798; CHECK:       vector.ph:
799; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 7
800; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8
801; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
802; CHECK:       vector.body:
803; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
804; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i16 [ 0, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]
805; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 [[INDEX]], i32 [[N]])
806; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[INDEX]]
807; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[TMP0]] to <8 x i16>*
808; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* [[TMP1]], i32 2, <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> undef)
809; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i16, i16* [[Y:%.*]], i32 [[INDEX]]
810; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i16* [[TMP2]] to <8 x i16>*
811; CHECK-NEXT:    [[WIDE_MASKED_LOAD1:%.*]] = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* [[TMP3]], i32 2, <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> undef)
812; CHECK-NEXT:    [[TMP4:%.*]] = mul <8 x i16> [[WIDE_MASKED_LOAD1]], [[WIDE_MASKED_LOAD]]
813; CHECK-NEXT:    [[TMP5:%.*]] = select <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> [[TMP4]], <8 x i16> zeroinitializer
814; CHECK-NEXT:    [[TMP6:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[TMP5]])
815; CHECK-NEXT:    [[TMP7]] = add i16 [[TMP6]], [[VEC_PHI]]
816; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 8
817; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
818; CHECK-NEXT:    br i1 [[TMP8]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP10:!llvm.loop !.*]]
819; CHECK:       for.cond.cleanup:
820; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[TMP7]], [[VECTOR_BODY]] ]
821; CHECK-NEXT:    ret i16 [[R_0_LCSSA]]
822;
823entry:
824  %cmp11 = icmp sgt i32 %n, 0
825  br i1 %cmp11, label %for.body, label %for.cond.cleanup
826
827for.body:                                         ; preds = %entry, %for.body
828  %i.013 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
829  %r.012 = phi i16 [ %add, %for.body ], [ 0, %entry ]
830  %arrayidx = getelementptr inbounds i16, i16* %x, i32 %i.013
831  %0 = load i16, i16* %arrayidx, align 2
832  %arrayidx1 = getelementptr inbounds i16, i16* %y, i32 %i.013
833  %1 = load i16, i16* %arrayidx1, align 2
834  %mul = mul i16 %1, %0
835  %add = add i16 %mul, %r.012
836  %inc = add nuw nsw i32 %i.013, 1
837  %exitcond = icmp eq i32 %inc, %n
838  br i1 %exitcond, label %for.cond.cleanup, label %for.body
839
840for.cond.cleanup:                                 ; preds = %for.body, %entry
841  %r.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
842  ret i16 %r.0.lcssa
843}
844
845define signext i16 @mla_i8_i16(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
846; CHECK-LABEL: @mla_i8_i16(
847; CHECK-NEXT:  entry:
848; CHECK-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[N:%.*]], 0
849; CHECK-NEXT:    br i1 [[CMP11]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
850; CHECK:       vector.ph:
851; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 7
852; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8
853; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
854; CHECK:       vector.body:
855; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
856; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i16 [ 0, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]
857; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 [[INDEX]], i32 [[N]])
858; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[INDEX]]
859; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i8>*
860; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* [[TMP1]], i32 1, <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i8> undef)
861; CHECK-NEXT:    [[TMP2:%.*]] = zext <8 x i8> [[WIDE_MASKED_LOAD]] to <8 x i16>
862; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[Y:%.*]], i32 [[INDEX]]
863; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <8 x i8>*
864; CHECK-NEXT:    [[WIDE_MASKED_LOAD1:%.*]] = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* [[TMP4]], i32 1, <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i8> undef)
865; CHECK-NEXT:    [[TMP5:%.*]] = zext <8 x i8> [[WIDE_MASKED_LOAD1]] to <8 x i16>
866; CHECK-NEXT:    [[TMP6:%.*]] = mul nuw <8 x i16> [[TMP5]], [[TMP2]]
867; CHECK-NEXT:    [[TMP7:%.*]] = select <8 x i1> [[ACTIVE_LANE_MASK]], <8 x i16> [[TMP6]], <8 x i16> zeroinitializer
868; CHECK-NEXT:    [[TMP8:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[TMP7]])
869; CHECK-NEXT:    [[TMP9]] = add i16 [[TMP8]], [[VEC_PHI]]
870; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 8
871; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
872; CHECK-NEXT:    br i1 [[TMP10]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP11:!llvm.loop !.*]]
873; CHECK:       for.cond.cleanup:
874; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[TMP9]], [[VECTOR_BODY]] ]
875; CHECK-NEXT:    ret i16 [[R_0_LCSSA]]
876;
877entry:
878  %cmp11 = icmp sgt i32 %n, 0
879  br i1 %cmp11, label %for.body, label %for.cond.cleanup
880
881for.body:                                         ; preds = %entry, %for.body
882  %i.013 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
883  %r.012 = phi i16 [ %add, %for.body ], [ 0, %entry ]
884  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.013
885  %0 = load i8, i8* %arrayidx, align 1
886  %conv = zext i8 %0 to i16
887  %arrayidx1 = getelementptr inbounds i8, i8* %y, i32 %i.013
888  %1 = load i8, i8* %arrayidx1, align 1
889  %conv2 = zext i8 %1 to i16
890  %mul = mul nuw i16 %conv2, %conv
891  %add = add i16 %mul, %r.012
892  %inc = add nuw nsw i32 %i.013, 1
893  %exitcond = icmp eq i32 %inc, %n
894  br i1 %exitcond, label %for.cond.cleanup, label %for.body
895
896for.cond.cleanup:                                 ; preds = %for.body, %entry
897  %r.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
898  ret i16 %r.0.lcssa
899}
900
901define zeroext i8 @mla_i8_i8(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
902; CHECK-LABEL: @mla_i8_i8(
903; CHECK-NEXT:  entry:
904; CHECK-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[N:%.*]], 0
905; CHECK-NEXT:    br i1 [[CMP10]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
906; CHECK:       vector.ph:
907; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 15
908; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16
909; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
910; CHECK:       vector.body:
911; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
912; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i8 [ 0, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]
913; CHECK-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 [[INDEX]], i32 [[N]])
914; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i32 [[INDEX]]
915; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <16 x i8>*
916; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP1]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> undef)
917; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[Y:%.*]], i32 [[INDEX]]
918; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to <16 x i8>*
919; CHECK-NEXT:    [[WIDE_MASKED_LOAD1:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP3]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> undef)
920; CHECK-NEXT:    [[TMP4:%.*]] = mul <16 x i8> [[WIDE_MASKED_LOAD1]], [[WIDE_MASKED_LOAD]]
921; CHECK-NEXT:    [[TMP5:%.*]] = select <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> [[TMP4]], <16 x i8> zeroinitializer
922; CHECK-NEXT:    [[TMP6:%.*]] = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> [[TMP5]])
923; CHECK-NEXT:    [[TMP7]] = add i8 [[TMP6]], [[VEC_PHI]]
924; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 16
925; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
926; CHECK-NEXT:    br i1 [[TMP8]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], [[LOOP12:!llvm.loop !.*]]
927; CHECK:       for.cond.cleanup:
928; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[TMP7]], [[VECTOR_BODY]] ]
929; CHECK-NEXT:    ret i8 [[R_0_LCSSA]]
930;
931entry:
932  %cmp10 = icmp sgt i32 %n, 0
933  br i1 %cmp10, label %for.body, label %for.cond.cleanup
934
935for.body:                                         ; preds = %entry, %for.body
936  %i.012 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
937  %r.011 = phi i8 [ %add, %for.body ], [ 0, %entry ]
938  %arrayidx = getelementptr inbounds i8, i8* %x, i32 %i.012
939  %0 = load i8, i8* %arrayidx, align 1
940  %arrayidx1 = getelementptr inbounds i8, i8* %y, i32 %i.012
941  %1 = load i8, i8* %arrayidx1, align 1
942  %mul = mul i8 %1, %0
943  %add = add i8 %mul, %r.011
944  %inc = add nuw nsw i32 %i.012, 1
945  %exitcond = icmp eq i32 %inc, %n
946  br i1 %exitcond, label %for.cond.cleanup, label %for.body
947
948for.cond.cleanup:                                 ; preds = %for.body, %entry
949  %r.0.lcssa = phi i8 [ 0, %entry ], [ %add, %for.body ]
950  ret i8 %r.0.lcssa
951}
952
953attributes #0 = { "target-features"="+mve" }
954