1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -O3                   -S < %s  | FileCheck %s
3; RUN: opt -passes='default<O3>' -S < %s  | FileCheck %s
4
5target triple = "x86_64--"
6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
7
8; PR41813 - https://bugs.llvm.org/show_bug.cgi?id=41813
9
10define <4 x float> @hadd_reverse_v4f32(<4 x float> %a, <4 x float> %b) #0 {
11; CHECK-LABEL: @hadd_reverse_v4f32(
12; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i32> <i32 3, i32 1, i32 7, i32 5>
13; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 2, i32 0, i32 6, i32 4>
14; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
15; CHECK-NEXT:    ret <4 x float> [[TMP3]]
16;
17  %shuffle = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
18  %shuffle1 = shufflevector <4 x float> %b, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
19  %vecext = extractelement <4 x float> %shuffle, i32 0
20  %vecext2 = extractelement <4 x float> %shuffle, i32 1
21  %add = fadd float %vecext, %vecext2
22  %vecinit = insertelement <4 x float> undef, float %add, i32 0
23  %vecext3 = extractelement <4 x float> %shuffle, i32 2
24  %vecext4 = extractelement <4 x float> %shuffle, i32 3
25  %add5 = fadd float %vecext3, %vecext4
26  %vecinit6 = insertelement <4 x float> %vecinit, float %add5, i32 1
27  %vecext7 = extractelement <4 x float> %shuffle1, i32 0
28  %vecext8 = extractelement <4 x float> %shuffle1, i32 1
29  %add9 = fadd float %vecext7, %vecext8
30  %vecinit10 = insertelement <4 x float> %vecinit6, float %add9, i32 2
31  %vecext11 = extractelement <4 x float> %shuffle1, i32 2
32  %vecext12 = extractelement <4 x float> %shuffle1, i32 3
33  %add13 = fadd float %vecext11, %vecext12
34  %vecinit14 = insertelement <4 x float> %vecinit10, float %add13, i32 3
35  ret <4 x float> %vecinit14
36}
37
38define <4 x float> @reverse_hadd_v4f32(<4 x float> %a, <4 x float> %b) #0 {
39; CHECK-LABEL: @reverse_hadd_v4f32(
40; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[B:%.*]], <4 x float> [[A:%.*]], <4 x i32> <i32 2, i32 0, i32 6, i32 4>
41; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[B]], <4 x float> [[A]], <4 x i32> <i32 3, i32 1, i32 7, i32 5>
42; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
43; CHECK-NEXT:    ret <4 x float> [[TMP3]]
44;
45  %vecext = extractelement <4 x float> %a, i32 0
46  %vecext1 = extractelement <4 x float> %a, i32 1
47  %add = fadd float %vecext, %vecext1
48  %vecinit = insertelement <4 x float> undef, float %add, i32 0
49  %vecext2 = extractelement <4 x float> %a, i32 2
50  %vecext3 = extractelement <4 x float> %a, i32 3
51  %add4 = fadd float %vecext2, %vecext3
52  %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
53  %vecext6 = extractelement <4 x float> %b, i32 0
54  %vecext7 = extractelement <4 x float> %b, i32 1
55  %add8 = fadd float %vecext6, %vecext7
56  %vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 2
57  %vecext10 = extractelement <4 x float> %b, i32 2
58  %vecext11 = extractelement <4 x float> %b, i32 3
59  %add12 = fadd float %vecext10, %vecext11
60  %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
61  %shuffle = shufflevector <4 x float> %vecinit13, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
62  ret <4 x float> %shuffle
63}
64
65define <8 x float> @hadd_reverse_v8f32(<8 x float> %a, <8 x float> %b) #0 {
66; CHECK-LABEL: @hadd_reverse_v8f32(
67; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 7, i32 5, i32 15, i32 13, i32 3, i32 1, i32 11, i32 9>
68; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 6, i32 4, i32 14, i32 12, i32 2, i32 0, i32 10, i32 8>
69; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
70; CHECK-NEXT:    ret <8 x float> [[TMP3]]
71;
72  %shuffle = shufflevector <8 x float> %a, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
73  %shuffle1 = shufflevector <8 x float> %b, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
74  %vecext = extractelement <8 x float> %shuffle, i32 0
75  %vecext2 = extractelement <8 x float> %shuffle, i32 1
76  %add = fadd float %vecext, %vecext2
77  %vecinit = insertelement <8 x float> undef, float %add, i32 0
78  %vecext3 = extractelement <8 x float> %shuffle, i32 2
79  %vecext4 = extractelement <8 x float> %shuffle, i32 3
80  %add5 = fadd float %vecext3, %vecext4
81  %vecinit6 = insertelement <8 x float> %vecinit, float %add5, i32 1
82  %vecext7 = extractelement <8 x float> %shuffle1, i32 0
83  %vecext8 = extractelement <8 x float> %shuffle1, i32 1
84  %add9 = fadd float %vecext7, %vecext8
85  %vecinit10 = insertelement <8 x float> %vecinit6, float %add9, i32 2
86  %vecext11 = extractelement <8 x float> %shuffle1, i32 2
87  %vecext12 = extractelement <8 x float> %shuffle1, i32 3
88  %add13 = fadd float %vecext11, %vecext12
89  %vecinit14 = insertelement <8 x float> %vecinit10, float %add13, i32 3
90  %vecext15 = extractelement <8 x float> %shuffle, i32 4
91  %vecext16 = extractelement <8 x float> %shuffle, i32 5
92  %add17 = fadd float %vecext15, %vecext16
93  %vecinit18 = insertelement <8 x float> %vecinit14, float %add17, i32 4
94  %vecext19 = extractelement <8 x float> %shuffle, i32 6
95  %vecext20 = extractelement <8 x float> %shuffle, i32 7
96  %add21 = fadd float %vecext19, %vecext20
97  %vecinit22 = insertelement <8 x float> %vecinit18, float %add21, i32 5
98  %vecext23 = extractelement <8 x float> %shuffle1, i32 4
99  %vecext24 = extractelement <8 x float> %shuffle1, i32 5
100  %add25 = fadd float %vecext23, %vecext24
101  %vecinit26 = insertelement <8 x float> %vecinit22, float %add25, i32 6
102  %vecext27 = extractelement <8 x float> %shuffle1, i32 6
103  %vecext28 = extractelement <8 x float> %shuffle1, i32 7
104  %add29 = fadd float %vecext27, %vecext28
105  %vecinit30 = insertelement <8 x float> %vecinit26, float %add29, i32 7
106  ret <8 x float> %vecinit30
107}
108
109define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #0 {
110; CHECK-LABEL: @reverse_hadd_v8f32(
111; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
112; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
113; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
114; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
115; CHECK-NEXT:    ret <8 x float> [[SHUFFLE]]
116;
117  %vecext = extractelement <8 x float> %a, i32 0
118  %vecext1 = extractelement <8 x float> %a, i32 1
119  %add = fadd float %vecext, %vecext1
120  %vecinit = insertelement <8 x float> undef, float %add, i32 0
121  %vecext2 = extractelement <8 x float> %a, i32 2
122  %vecext3 = extractelement <8 x float> %a, i32 3
123  %add4 = fadd float %vecext2, %vecext3
124  %vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 1
125  %vecext6 = extractelement <8 x float> %b, i32 0
126  %vecext7 = extractelement <8 x float> %b, i32 1
127  %add8 = fadd float %vecext6, %vecext7
128  %vecinit9 = insertelement <8 x float> %vecinit5, float %add8, i32 2
129  %vecext10 = extractelement <8 x float> %b, i32 2
130  %vecext11 = extractelement <8 x float> %b, i32 3
131  %add12 = fadd float %vecext10, %vecext11
132  %vecinit13 = insertelement <8 x float> %vecinit9, float %add12, i32 3
133  %vecext14 = extractelement <8 x float> %a, i32 4
134  %vecext15 = extractelement <8 x float> %a, i32 5
135  %add16 = fadd float %vecext14, %vecext15
136  %vecinit17 = insertelement <8 x float> %vecinit13, float %add16, i32 4
137  %vecext18 = extractelement <8 x float> %a, i32 6
138  %vecext19 = extractelement <8 x float> %a, i32 7
139  %add20 = fadd float %vecext18, %vecext19
140  %vecinit21 = insertelement <8 x float> %vecinit17, float %add20, i32 5
141  %vecext22 = extractelement <8 x float> %b, i32 4
142  %vecext23 = extractelement <8 x float> %b, i32 5
143  %add24 = fadd float %vecext22, %vecext23
144  %vecinit25 = insertelement <8 x float> %vecinit21, float %add24, i32 6
145  %vecext26 = extractelement <8 x float> %b, i32 6
146  %vecext27 = extractelement <8 x float> %b, i32 7
147  %add28 = fadd float %vecext26, %vecext27
148  %vecinit29 = insertelement <8 x float> %vecinit25, float %add28, i32 7
149  %shuffle = shufflevector <8 x float> %vecinit29, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
150  ret <8 x float> %shuffle
151}
152
153attributes #0 = { "min-legal-vector-width"="128" "target-cpu"="btver2" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3" }
154