1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=thumbv8m.main %s -simplifycfg -S | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
3; RUN: opt -mtriple=thumbv8a %s -simplifycfg -S | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
4; RUN: opt -mtriple=armv8a %s -simplifycfg -S | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
5
6define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) {
7; CHECK-LABEL: @foo(
8; CHECK-NEXT:  entry:
9; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
10; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
11; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
12; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP1]]
13; CHECK-NEXT:    br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
14; CHECK:       cond.false:
15; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
16; CHECK-NEXT:    br label [[COND_END]]
17; CHECK:       cond.end:
18; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
19; CHECK-NEXT:    ret i32 [[COND]]
20;
21entry:
22  %cmp = icmp sgt i32 %d, 3
23  br i1 %cmp, label %cond.end, label %lor.lhs.false
24
25lor.lhs.false:
26  %add = add nsw i32 %c, %a
27  %cmp1 = icmp slt i32 %add, %b
28  br i1 %cmp1, label %cond.false, label %cond.end
29
30cond.false:
31  %0 = load i32, i32* %input, align 4
32  br label %cond.end
33
34cond.end:
35  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
36  ret i32 %cond
37}
38
39define i32 @foo_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) #0 {
40; CHECK-LABEL: @foo_minsize(
41; CHECK-NEXT:  entry:
42; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
43; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
44; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
45; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP1]]
46; CHECK-NEXT:    br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
47; CHECK:       cond.false:
48; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
49; CHECK-NEXT:    br label [[COND_END]]
50; CHECK:       cond.end:
51; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
52; CHECK-NEXT:    ret i32 [[COND]]
53;
54entry:
55  %cmp = icmp sgt i32 %d, 3
56  br i1 %cmp, label %cond.end, label %lor.lhs.false
57
58lor.lhs.false:
59  %add = add nsw i32 %c, %a
60  %cmp1 = icmp slt i32 %add, %b
61  br i1 %cmp1, label %cond.false, label %cond.end
62
63cond.false:
64  %0 = load i32, i32* %input, align 4
65  br label %cond.end
66
67cond.end:
68  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
69  ret i32 %cond
70}
71
72define i32 @foo_minsize_i64(i64 %a, i64 %b, i64 %c, i64 %d, i32* %input) #0 {
73; CHECK-LABEL: @foo_minsize_i64(
74; CHECK-NEXT:  entry:
75; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i64 [[D:%.*]], 3
76; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[C:%.*]], [[A:%.*]]
77; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i64 [[ADD]], [[B:%.*]]
78; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP1]]
79; CHECK-NEXT:    br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
80; CHECK:       cond.false:
81; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
82; CHECK-NEXT:    br label [[COND_END]]
83; CHECK:       cond.end:
84; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
85; CHECK-NEXT:    ret i32 [[COND]]
86;
87entry:
88  %cmp = icmp sgt i64 %d, 3
89  br i1 %cmp, label %cond.end, label %lor.lhs.false
90
91lor.lhs.false:
92  %add = add nsw i64 %c, %a
93  %cmp1 = icmp slt i64 %add, %b
94  br i1 %cmp1, label %cond.false, label %cond.end
95
96cond.false:
97  %0 = load i32, i32* %input, align 4
98  br label %cond.end
99
100cond.end:
101  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
102  ret i32 %cond
103}
104
105define i32 @or_predicate(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) {
106; CHECK-LABEL: @or_predicate(
107; CHECK-NEXT:  entry:
108; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
109; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
110; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
111; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
112; CHECK-NEXT:    br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
113; CHECK:       cond.false:
114; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
115; CHECK-NEXT:    br label [[COND_END]]
116; CHECK:       cond.end:
117; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
118; CHECK-NEXT:    ret i32 [[COND]]
119;
120entry:
121  %cmp = icmp sgt i32 %d, 3
122  br i1 %cmp, label %cond.end, label %lor.lhs.false
123
124lor.lhs.false:
125  %add = add nsw i32 %c, %a
126  %cmp1 = icmp slt i32 %add, %b
127  br i1 %cmp1, label %cond.end, label %cond.false
128
129cond.false:
130  %0 = load i32, i32* %input, align 4
131  br label %cond.end
132
133cond.end:
134  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
135  ret i32 %cond
136}
137
138define i32 @or_invert_predicate(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) {
139; CHECK-LABEL: @or_invert_predicate(
140; CHECK-NEXT:  entry:
141; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
142; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
143; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
144; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
145; CHECK-NEXT:    br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
146; CHECK:       cond.false:
147; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
148; CHECK-NEXT:    br label [[COND_END]]
149; CHECK:       cond.end:
150; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
151; CHECK-NEXT:    ret i32 [[COND]]
152;
153entry:
154  %cmp = icmp sgt i32 %d, 3
155  br i1 %cmp, label %lor.lhs.false, label %cond.end
156
157lor.lhs.false:
158  %add = add nsw i32 %c, %a
159  %cmp1 = icmp slt i32 %add, %b
160  br i1 %cmp1, label %cond.end, label %cond.false
161
162cond.false:
163  %0 = load i32, i32* %input, align 4
164  br label %cond.end
165
166cond.end:
167  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
168  ret i32 %cond
169}
170
171define i32 @or_predicate_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) #0 {
172; THUMB-LABEL: @or_predicate_minsize(
173; THUMB-NEXT:  entry:
174; THUMB-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
175; THUMB-NEXT:    br i1 [[CMP]], label [[COND_END:%.*]], label [[LOR_LHS_FALSE:%.*]]
176; THUMB:       lor.lhs.false:
177; THUMB-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
178; THUMB-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
179; THUMB-NEXT:    br i1 [[CMP1]], label [[COND_END]], label [[COND_FALSE:%.*]]
180; THUMB:       cond.false:
181; THUMB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
182; THUMB-NEXT:    br label [[COND_END]]
183; THUMB:       cond.end:
184; THUMB-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
185; THUMB-NEXT:    ret i32 [[COND]]
186;
187; ARM-LABEL: @or_predicate_minsize(
188; ARM-NEXT:  entry:
189; ARM-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
190; ARM-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
191; ARM-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
192; ARM-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
193; ARM-NEXT:    br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
194; ARM:       cond.false:
195; ARM-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
196; ARM-NEXT:    br label [[COND_END]]
197; ARM:       cond.end:
198; ARM-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
199; ARM-NEXT:    ret i32 [[COND]]
200;
201entry:
202  %cmp = icmp sgt i32 %d, 3
203  br i1 %cmp, label %cond.end, label %lor.lhs.false
204
205lor.lhs.false:
206  %add = add nsw i32 %c, %a
207  %cmp1 = icmp slt i32 %add, %b
208  br i1 %cmp1, label %cond.end, label %cond.false
209
210cond.false:
211  %0 = load i32, i32* %input, align 4
212  br label %cond.end
213
214cond.end:
215  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
216  ret i32 %cond
217}
218
219define i32 @or_invert_predicate_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) #0 {
220; THUMB-LABEL: @or_invert_predicate_minsize(
221; THUMB-NEXT:  entry:
222; THUMB-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
223; THUMB-NEXT:    br i1 [[CMP]], label [[LOR_LHS_FALSE:%.*]], label [[COND_END:%.*]]
224; THUMB:       lor.lhs.false:
225; THUMB-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
226; THUMB-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
227; THUMB-NEXT:    br i1 [[CMP1]], label [[COND_END]], label [[COND_FALSE:%.*]]
228; THUMB:       cond.false:
229; THUMB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
230; THUMB-NEXT:    br label [[COND_END]]
231; THUMB:       cond.end:
232; THUMB-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
233; THUMB-NEXT:    ret i32 [[COND]]
234;
235; ARM-LABEL: @or_invert_predicate_minsize(
236; ARM-NEXT:  entry:
237; ARM-NEXT:    [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
238; ARM-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
239; ARM-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
240; ARM-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
241; ARM-NEXT:    br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
242; ARM:       cond.false:
243; ARM-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
244; ARM-NEXT:    br label [[COND_END]]
245; ARM:       cond.end:
246; ARM-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
247; ARM-NEXT:    ret i32 [[COND]]
248;
249entry:
250  %cmp = icmp sgt i32 %d, 3
251  br i1 %cmp, label %lor.lhs.false, label %cond.end
252
253lor.lhs.false:
254  %add = add nsw i32 %c, %a
255  %cmp1 = icmp slt i32 %add, %b
256  br i1 %cmp1, label %cond.end, label %cond.false
257
258cond.false:
259  %0 = load i32, i32* %input, align 4
260  br label %cond.end
261
262cond.end:
263  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
264  ret i32 %cond
265}
266
267define i32 @or_xor_predicate(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) {
268; CHECK-LABEL: @or_xor_predicate(
269; CHECK-NEXT:  entry:
270; CHECK-NEXT:    [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
271; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
272; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
273; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP_NOT]], [[CMP1]]
274; CHECK-NEXT:    br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
275; CHECK:       cond.false:
276; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
277; CHECK-NEXT:    br label [[COND_END]]
278; CHECK:       cond.end:
279; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
280; CHECK-NEXT:    ret i32 [[COND]]
281;
282entry:
283  br i1 %cmp, label %lor.lhs.false, label %cond.end
284
285lor.lhs.false:
286  %add = add nsw i32 %c, %a
287  %cmp1 = icmp slt i32 %add, %b
288  br i1 %cmp1, label %cond.end, label %cond.false
289
290cond.false:
291  %0 = load i32, i32* %input, align 4
292  br label %cond.end
293
294cond.end:
295  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
296  ret i32 %cond
297}
298
299define i32 @or_xor_predicate_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) #0 {
300; THUMB-LABEL: @or_xor_predicate_minsize(
301; THUMB-NEXT:  entry:
302; THUMB-NEXT:    br i1 [[CMP:%.*]], label [[LOR_LHS_FALSE:%.*]], label [[COND_END:%.*]]
303; THUMB:       lor.lhs.false:
304; THUMB-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
305; THUMB-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
306; THUMB-NEXT:    br i1 [[CMP1]], label [[COND_END]], label [[COND_FALSE:%.*]]
307; THUMB:       cond.false:
308; THUMB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
309; THUMB-NEXT:    br label [[COND_END]]
310; THUMB:       cond.end:
311; THUMB-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
312; THUMB-NEXT:    ret i32 [[COND]]
313;
314; ARM-LABEL: @or_xor_predicate_minsize(
315; ARM-NEXT:  entry:
316; ARM-NEXT:    [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
317; ARM-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
318; ARM-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
319; ARM-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP_NOT]], [[CMP1]]
320; ARM-NEXT:    br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
321; ARM:       cond.false:
322; ARM-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
323; ARM-NEXT:    br label [[COND_END]]
324; ARM:       cond.end:
325; ARM-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
326; ARM-NEXT:    ret i32 [[COND]]
327;
328entry:
329  br i1 %cmp, label %lor.lhs.false, label %cond.end
330
331lor.lhs.false:
332  %add = add nsw i32 %c, %a
333  %cmp1 = icmp slt i32 %add, %b
334  br i1 %cmp1, label %cond.end, label %cond.false
335
336cond.false:
337  %0 = load i32, i32* %input, align 4
338  br label %cond.end
339
340cond.end:
341  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
342  ret i32 %cond
343}
344
345define i32 @and_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) {
346; CHECK-LABEL: @and_xor(
347; CHECK-NEXT:  entry:
348; CHECK-NEXT:    [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
349; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
350; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
351; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP_NOT]], [[CMP1]]
352; CHECK-NEXT:    br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
353; CHECK:       cond.false:
354; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
355; CHECK-NEXT:    br label [[COND_END]]
356; CHECK:       cond.end:
357; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
358; CHECK-NEXT:    ret i32 [[COND]]
359;
360entry:
361  br i1 %cmp, label %cond.end, label %lor.lhs.false
362
363lor.lhs.false:
364  %add = add nsw i32 %c, %a
365  %cmp1 = icmp slt i32 %add, %b
366  br i1 %cmp1, label %cond.false, label %cond.end
367
368cond.false:
369  %0 = load i32, i32* %input, align 4
370  br label %cond.end
371
372cond.end:
373  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
374  ret i32 %cond
375}
376
377define i32 @and_xor_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) #0 {
378; THUMB-LABEL: @and_xor_minsize(
379; THUMB-NEXT:  entry:
380; THUMB-NEXT:    br i1 [[CMP:%.*]], label [[COND_END:%.*]], label [[LOR_LHS_FALSE:%.*]]
381; THUMB:       lor.lhs.false:
382; THUMB-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
383; THUMB-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
384; THUMB-NEXT:    br i1 [[CMP1]], label [[COND_FALSE:%.*]], label [[COND_END]]
385; THUMB:       cond.false:
386; THUMB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
387; THUMB-NEXT:    br label [[COND_END]]
388; THUMB:       cond.end:
389; THUMB-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
390; THUMB-NEXT:    ret i32 [[COND]]
391;
392; ARM-LABEL: @and_xor_minsize(
393; ARM-NEXT:  entry:
394; ARM-NEXT:    [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
395; ARM-NEXT:    [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
396; ARM-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
397; ARM-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP_NOT]], [[CMP1]]
398; ARM-NEXT:    br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
399; ARM:       cond.false:
400; ARM-NEXT:    [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
401; ARM-NEXT:    br label [[COND_END]]
402; ARM:       cond.end:
403; ARM-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
404; ARM-NEXT:    ret i32 [[COND]]
405;
406entry:
407  br i1 %cmp, label %cond.end, label %lor.lhs.false
408
409lor.lhs.false:
410  %add = add nsw i32 %c, %a
411  %cmp1 = icmp slt i32 %add, %b
412  br i1 %cmp1, label %cond.false, label %cond.end
413
414cond.false:
415  %0 = load i32, i32* %input, align 4
416  br label %cond.end
417
418cond.end:
419  %cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
420  ret i32 %cond
421}
422
423attributes #0 = { minsize optsize }
424